ATCDC: Digimorf, Day 59, The project SEGA SG-1000 Emulator on PSoC62S4 Pioneer kit, part 12

RE: ATCDC: Digimorf, Day 59, The project SEGA SG-1000 Emulator on PSoC62S4 Pioneer kit, part 12

Digimorf — Thu, 04 May 2023 07:41:15 GMT

Hi, I had some time to spend in R&D yesterday, and I tried to investigate the jitter caused apparently by the access to the SRAM at the same time by the cores.

I have plug this "PSoC6 Gaming System" (Iam making fun of it) to my big TV and I noticed that the jitter involves the starting point of the scanline, since it seems that it translates randomly when things in the game moves heavily. So it's the entire line that translates, not single pixels. All this things suggest me that the DMA transfers are not really affected by the arbitration, otherwise the line would have been shrink or stretched irregulairly. Maybe something happens when the Inerrupt of the scanline fires.

This sounds weird to me because the two cores have two indipendent interrupt systems. But wait, the vector table is located into the SRAM! The startup code *.s takes care of copying the table from Flash to SRAM. So, is it possible that the jump action to the ISR location is influenced by a delay during the fetching of the address from the vector table in the SRAM?

I should leave the table in the Flash, but it seems a bit tricky because all the memory map in the linker file is designed accordingly to the vector table located in the SRAM.

Probably I will work more on it in the next days for fun, but I wanted to bring your attention to this potential issue for a dual-core design.

RE: ATCDC: Digimorf, Day 59, The project SEGA SG-1000 Emulator on PSoC62S4 Pioneer kit, part 12

ljking — Mon, 01 May 2023 16:46:05 GMT

Hi @digimorph

Sorry for the delay. I did some research on this topic. Each SRAM block has two ports, a High Speed port, and a Low Speed port. The bus masters on each port have a 'priority' which is set in the PROT_SMPU_MSx_CTL[PRIO] registers described in the Technical Reference Manual (TRM). What is missing from the TRM/Datasheet is the mapping of 'x' to the various bus masters. Here is the mapping for 'x' and the bus masters:

0 - CM0+

1 - Crypto

2 - DW0

3 - DW1

4 - DMA

5 - DW0 (slow)

6 - DW1 (slow)

14 - CM4 (cortex M4)

16 - DAP (debug)

In your case I 'think' you need to change the priority in the PROT_SMPU_MS4_CTL[PRIO] register, but I haven't tried it so I am not positive this will work.

RE: ATCDC: Digimorf, Day 59, The project SEGA SG-1000 Emulator on PSoC62S4 Pioneer kit, part 12

dougw — Thu, 27 Apr 2023 16:49:21 GMT

It sounds like you need dual port RAM...