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RE: PSoC6S4 Vector table of the cm0+ in flash.

Digimorf — Wed, 10 May 2023 07:14:36 GMT

Thanks for the support. I think I will try first to leave vectors in the flash. I can't understand why this is not the standard configuration.

Anyway the PDL documentation shows how to configure an interrupt to use the vector table in the flash, but that doesn't work for me. Probably I am missing something.

https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysint.html

PSoC6S4 Vector table of the cm0+ in flash.

Digimorf — Tue, 09 May 2023 17:53:56 GMT

Has anyone tried to leave the vector table of the cm0+ in flash and configure an interrupt?

By default it is copied into SRAM. No doubt about it's faster to fetch the addresses of the IRQ handlers at runtime, but I need to check if the access to SRAM by both cores causes jitter in fetching the IRQ handlers.

I tried to customize the startup file of the cm0+, but something must be inherited by the PDL such as the ram_table_address.

Thanks

RE: PSoC6S4 Vector table of the cm0+ in flash.

misaz — Tue, 09 May 2023 21:21:28 GMT

Yes. SRAM access on different cores (or caused by DMA or otherm AHB masters) can influence interrupt latancy. I tested it on different PSoC for evaluating Profiler peripheral (which is unluckily not avalaible on part used in At The Core Design Challenge) and shown how SRAM accesses on one core affects performance of the other. For more details see my blog: PSoC 6 Pioneer Kit Roadtest - Project 6 - Profiler

Interrupt latency is affected by multiple factors and vector table storage memory (and it's utilization) is one of them. It is very hard to achieve zero jitter on interrupt latency on Cortex-M. Some points why is it hard are described in ARM article: https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/beginner-guide-on-interrupt-latency-and-interrupt-latency-of-the-arm-cortex-m-processors

RE: PSoC6S4 Vector table of the cm0+ in flash.

ljking — Tue, 09 May 2023 20:32:16 GMT

That was my thinking also, but I don't want to assume that is the correct answer. For an example, a single controller could control two 32k blocks. Until I get to see the answer formally documented, I don't want to give you possibly in-accurate information.

If your problem is actually SRAM access contention (which seems like a reasonable guess), then moving the video buffers to the highest addresses in memory, and the vectors to the lowest addresses should give you some information.

Is it possible the CM0+ is servicing some higher priority interrupt, and you have to wait for that to complete before it starts the video interrupt? (just throwing out other ideas to explore).

RE: PSoC6S4 Vector table of the cm0+ in flash.

Digimorf — Tue, 09 May 2023 20:21:02 GMT

Thank you for sharing this information. Are you referring to what is said in the datasheet:

"■ SRAM Up to 128 KB of SRAM is provided. Power control and retention granularity is implemented in 32 KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode."

In this case there should be 4 controllers...

RE: PSoC6S4 Vector table of the cm0+ in flash.

ljking — Tue, 09 May 2023 19:00:57 GMT

There are actually several independent SRAM blocks and controllers inside the part (it is not just a single large SRAM). if you put the Video buffer in a different SRAM block from the vectors I suspect this will help. Unfortunately the datasheet and Technical Reference manuals do not tell you the addresses of the SRAM blocks. I have raised a documentation bug against this oversight, but I can't tell you when updated documentation will be released. I would trial and error moving the locations of the video buffers in SRAM to see if that helps.

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Sun, 19 Mar 2023 19:09:34 GMT

FINALLY!

Actually, the code works, what is wrong is the GPIO output port. I assigned it in the wrong way.

// WRONG
// GPIO_PRT_Type* scanline_rgb_port = GPIO_PRT10;

// CORRECT
uint8_t *scanline_rgb_port = (uint8_t *)(&GPIO_PRT10->OUT);

And in the setup of the DMAC descriptor the destination address:

  Cy_DMAC_Descriptor_SetDstAddress(&scanline_pixel_dma_descriptor, (uint8_t*)(scanline_rgb_port));

CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Wed, 15 Mar 2023 23:51:41 GMT

Hello,

I am working on the configuration of a DMAC channel for streaming data bytes from a buffer to the GPIO port 10, using only GPIOs from 0 to 2. I think I am missing something but I really can't make it work.

Since I am learning for now I am triggering the DMA by simply enabling the block, next I will trigger it with a CC0 of a counter. But, let's see what I got so far.

I have started an "Empty Project" from the getting started section. Then in the "Device Configurator" I simply set the DMAC channel 0 for a transfer of 1 byte.

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:a62d9f17-0897-49bb-8708-6f333a936bdd:type=c_cpp&text=%2F%2A%20NOTE%3A%20This%20is%20a%20preview%20only.%20It%20combines%20elements%20of%20the%0D%0A%20%2A%20cycfg_dmas.c%20and%20cycfg_dmas.h%20files%20located%20in%20the%20folder%0D%0A%20%2A%20C%3A%2FUsers%2FFrancesco%2Fmtw%2FEmpty_App_1%2Fbsps%2FTARGET_APP_CY8CKIT-062S4%2Fconfig%2FGeneratedSource.%0D%0A%20%2A%2F%0D%0A%0D%0A%23include%20%22cy_dmac.h%22%0D%0A%23if%20defined%20%28CY_USING_HAL%29%0D%0A%20%20%20%20%23include%20%22cyhal_hwmgr.h%22%0D%0A%23endif%20%2F%2Fdefined%20%28CY_USING_HAL%29%0D%0A%0D%0A%23define%20cpuss_0_dmac_0_chan_0_HW%20DMAC%0D%0A%23define%20cpuss_0_dmac_0_chan_0_CHANNEL%200U%0D%0A%23define%20cpuss_0_dmac_0_chan_0_IRQ%20cpuss_interrupts_dmac_0_IRQn%0D%0A%0D%0Acy_stc_dmac_descriptor_config_t%20cpuss_0_dmac_0_chan_0_Descriptor_0_config%20%3D%20%0D%0A%7B%0D%0A%20%20%20%20.retrigger%20%3D%20CY_DMAC_RETRIG_IM%2C%0D%0A%20%20%20%20.interruptType%20%3D%20CY_DMAC_1ELEMENT%2C%0D%0A%20%20%20%20.triggerOutType%20%3D%20CY_DMAC_1ELEMENT%2C%0D%0A%20%20%20%20.channelState%20%3D%20CY_DMAC_CHANNEL_ENABLED%2C%0D%0A%20%20%20%20.triggerInType%20%3D%20CY_DMAC_1ELEMENT%2C%0D%0A%20%20%20%20.dataPrefetch%20%3D%20false%2C%0D%0A%20%20%20%20.dataSize%20%3D%20CY_DMAC_WORD%2C%0D%0A%20%20%20%20.srcTransferSize%20%3D%20CY_DMAC_TRANSFER_SIZE_WORD%2C%0D%0A%20%20%20%20.dstTransferSize%20%3D%20CY_DMAC_TRANSFER_SIZE_WORD%2C%0D%0A%20%20%20%20.descriptorType%20%3D%20CY_DMAC_SINGLE_TRANSFER%2C%0D%0A%20%20%20%20.srcAddress%20%3D%20NULL%2C%0D%0A%20%20%20%20.dstAddress%20%3D%20NULL%2C%0D%0A%20%20%20%20.srcXincrement%20%3D%200%2C%0D%0A%20%20%20%20.dstXincrement%20%3D%200%2C%0D%0A%20%20%20%20.xCount%20%3D%201%2C%0D%0A%20%20%20%20.srcYincrement%20%3D%201%2C%0D%0A%20%20%20%20.dstYincrement%20%3D%201%2C%0D%0A%20%20%20%20.yCount%20%3D%201%2C%0D%0A%20%20%20%20.nextDescriptor%20%3D%20NULL%2C%0D%0A%7D%3B%0D%0Acy_stc_dmac_descriptor_t%20cpuss_0_dmac_0_chan_0_Descriptor_0%20%3D%20%0D%0A%7B%0D%0A%20%20%20%20.ctl%20%3D%200UL%2C%0D%0A%20%20%20%20.src%20%3D%200UL%2C%0D%0A%20%20%20%20.dst%20%3D%200UL%2C%0D%0A%20%20%20%20.xSize%20%3D%200UL%2C%0D%0A%20%20%20%20.xIncr%20%3D%200UL%2C%0D%0A%20%20%20%20.ySize%20%3D%200UL%2C%0D%0A%20%20%20%20.yIncr%20%3D%200UL%2C%0D%0A%20%20%20%20.nextPtr%20%3D%200UL%2C%0D%0A%7D%3B%0D%0Acy_stc_dmac_channel_config_t%20cpuss_0_dmac_0_chan_0_channelConfig%20%3D%20%0D%0A%7B%0D%0A%20%20%20%20.descriptor%20%3D%20%26cpuss_0_dmac_0_chan_0_Descriptor_0%2C%0D%0A%20%20%20%20.priority%20%3D%203%2C%0D%0A%20%20%20%20.enable%20%3D%20false%2C%0D%0A%20%20%20%20.bufferable%20%3D%20false%2C%0D%0A%7D%3B%0D%0A%23if%20defined%20%28CY_USING_HAL%29%0D%0A%20%20%20%20const%20cyhal_resource_inst_t%20cpuss_0_dmac_0_chan_0_obj%20%3D%20%0D%0A%20%20%20%20%7B%0D%0A%20%20%20%20%20%20%20%20.type%20%3D%20CYHAL_RSC_DMA%2C%0D%0A%20%20%20%20%20%20%20%20.block_num%20%3D%202U%2C%0D%0A%20%20%20%20%20%20%20%20.channel_num%20%3D%20cpuss_0_dmac_0_chan_0_CHANNEL%2C%0D%0A%20%20%20%20%7D%3B%0D%0A%23endif%20%2F%2Fdefined%20%28CY_USING_HAL%29%0D%0A%0D%0A%0D%0Avoid%20reserve_cycfg_dmas%28void%29%0D%0A%7B%0D%0A%23if%20defined%20%28CY_USING_HAL%29%0D%0A%20%20%20%20cyhal_hwmgr_reserve%28%26cpuss_0_dmac_0_chan_0_obj%29%3B%0D%0A%23endif%20%2F%2Fdefined%20%28CY_USING_HAL%29%0D%0A%7D%0D%0A]

The three GPIOs P10_0..2 are configured as:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:8026dfaa-28ad-407e-858b-e00767a2f1f6:type=c_cpp&text=const%20cy_stc_gpio_pin_config_t%20CYBSP_A0_config%20%3D%20%0A%7B%0A%20%20%20%20.outVal%20%3D%200%2C%0A%20%20%20%20.driveMode%20%3D%20CY_GPIO_DM_STRONG_IN_OFF%2C%0A%20%20%20%20.hsiom%20%3D%20CYBSP_A0_HSIOM%2C%0A%20%20%20%20.intEdge%20%3D%20CY_GPIO_INTR_DISABLE%2C%0A%20%20%20%20.intMask%20%3D%200UL%2C%0A%20%20%20%20.vtrip%20%3D%20CY_GPIO_VTRIP_CMOS%2C%0A%20%20%20%20.slewRate%20%3D%20CY_GPIO_SLEW_FAST%2C%0A%20%20%20%20.driveSel%20%3D%20CY_GPIO_DRIVE_1_2%2C%0A%20%20%20%20.vregEn%20%3D%200UL%2C%0A%20%20%20%20.ibufMode%20%3D%200UL%2C%0A%20%20%20%20.vtripSel%20%3D%200UL%2C%0A%20%20%20%20.vrefSel%20%3D%200UL%2C%0A%20%20%20%20.vohSel%20%3D%200UL%2C%0A%7D%3B]

Then in the main.c I set the destination and source:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:9b514f7b-82b5-4e4c-a832-625f46f2722d:type=c_cpp&text=%23include%20%22cyhal.h%22%0A%23include%20%22cybsp.h%22%0A%0A%23define%20scanline_dma_HW%20%20%20%20%20%20%20%20%20%20%20%20%20cpuss_0_dmac_0_chan_0_HW%0A%23define%20scanline_dma_descriptor%20%20%20%20%20cpuss_0_dmac_0_chan_0_Descriptor_0%0A%23define%20scanline_dma_descriptor_cfg%20cpuss_0_dmac_0_chan_0_Descriptor_0_config%0A%23define%20scanline_dma_CH%20%20%20%20%20%20%20%20%20%20%20%20%20cpuss_0_dmac_0_chan_0_CHANNEL%0A%23define%20scanline_dma_CH_cfg%20%20%20%20%20%20%20%20%20cpuss_0_dmac_0_chan_0_channelConfig%0A%0Auint32_t%20pix%20%3D%200x5%3B%0AGPIO_PRT_Type%2A%20scanline_rgb_port%20%3D%20GPIO_PRT10%3B%0A%0A%0Aint%20main%28void%29%0A%7B%0A%20%20%20%20cy_rslt_t%20result%3B%0A%0A%23if%20defined%20%28CY_DEVICE_SECURE%29%0A%20%20%20%20cyhal_wdt_t%20wdt_obj%3B%0A%0A%20%20%20%20%2F%2A%20Clear%20watchdog%20timer%20so%20that%20it%20doesn%27t%20trigger%20a%20reset%20%2A%2F%0A%20%20%20%20result%20%3D%20cyhal_wdt_init%28%26wdt_obj%2C%20cyhal_wdt_get_max_timeout_ms%28%29%29%3B%0A%20%20%20%20CY_ASSERT%28CY_RSLT_SUCCESS%20%3D%3D%20result%29%3B%0A%20%20%20%20cyhal_wdt_free%28%26wdt_obj%29%3B%0A%23endif%0A%0A%20%20%20%20%2F%2A%20Initialize%20the%20device%20and%20board%20peripherals%20%2A%2F%0A%20%20%20%20result%20%3D%20cybsp_init%28%29%3B%0A%0A%20%20%20%20%2F%2A%20Board%20init%20failed.%20Stop%20program%20execution%20%2A%2F%0A%20%20%20%20if%20%28result%20%21%3D%20CY_RSLT_SUCCESS%29%0A%20%20%20%20%7B%0A%20%20%20%20%20%20%20%20CY_ASSERT%280%29%3B%0A%20%20%20%20%7D%0A%0A%20%20%20%20%2F%2A%20Enable%20global%20interrupts%20%2A%2F%0A%20%20%20%20__enable_irq%28%29%3B%0A%0A%20%20%20%20Cy_DMAC_Descriptor_Init%28%26scanline_dma_descriptor%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%26scanline_dma_descriptor_cfg%29%3B%0A%0A%20%20%20%20Cy_DMAC_Descriptor_SetSrcAddress%28%26scanline_dma_descriptor%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%28void%2A%29%26pix%29%3B%0A%0A%20%20%20%20Cy_DMAC_Descriptor_SetDstAddress%28%26scanline_dma_descriptor%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%28void%2A%29%28scanline_rgb_port-%3EOUT%29%29%3B%0A%0A%20%20%20%20Cy_DMAC_Channel_Init%28scanline_dma_HW%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20scanline_dma_CH%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%26scanline_dma_CH_cfg%29%3B%0A%0A%20%20%20%20Cy_DMAC_Channel_SetDescriptor%28scanline_dma_HW%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20scanline_dma_CH%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%26scanline_dma_descriptor%29%3B%0A%0A%20%20%20%20Cy_DMAC_Channel_Enable%28scanline_dma_HW%2C%0A%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20scanline_dma_CH%29%3B%0A%0A%20%20%20%20Cy_DMAC_Enable%28scanline_dma_HW%29%3B%0A%0A%20%20%20%20for%20%28%3B%3B%29%0A%20%20%20%20%7B%0A%0A%20%20%20%20%7D%0A%7D]

My Logic Analyzer should show signals 0 and 2 pulsing from low to high but nothing happens, I can't understand if the transfer doesn't start, or if the GPIO port is not correct for output.

I haven't been lucky in finding an example of the use of DMA on GPIOs, so I am asking here [emoticon:c4563cd7d5574777a71c318021cbbcc8]

Thank you.

RE: CY8C62 DMA from buffer to GPIO P10_0..2

misaz — Sat, 18 Mar 2023 10:51:18 GMT

Your DMA transfer most probably failed because of ilegal bus access.

I have faced similar problem. Issue is that GPIO OUT register prohibits byte (8-bit) and word (16-bit) AXI access and allows only double word (32-bit) access like most of PSoC6 registers do. I do not know about DMAC but DW cant do transformation of data and I have to use array of uint32_t with 3 bytes unsed instead of array of uint8_t.

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Sat, 18 Mar 2023 10:23:02 GMT

I have partially solved the problem, so if I need to create a fast copy width Dma I know what to do, but actually it seems not working when I address the destination of DMA to GPIO_PRT10->OUT.

-mumble mumble -

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Fri, 17 Mar 2023 13:49:56 GMT

[quote userid="245556" url="~/challenges-projects/design-challenges/at-the-core-design-challenge/f/forum/52607/cy8c62-dma-from-buffer-to-gpio-p10_0-2/207039"]In the Trigger multiplexer diagram, I saw that the CPUSS.Zero should be a software trigger connected to the DMAC block, but I wasn't able to find what this "Zero" means in the CPU SubSystem. [/quote]

Actually, the solution was there in front of me.

The Multiplexer Block Diagram shows the interconnections possible between the triggers of the peripherals. Here the white rabbit hole gets deeper because all these connections are fully programmable. This is a great surprise, another "like" for this microcontroller!

I discovered that the PDL offers the TrigMux (Trigger Multiplexer) driver, which offers the function to interconnect triggers, and FINALLY how to fire a software trigger on a specific line! That is what I wanted, damn three days of tests, research, and readings.

TrigMux PDL driver

The function needed to start the DMAC, channel 0 is:

if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_SwTrigger(TRIG_OUT_MUX_6_MDMA_TR_IN0, CY_TRIGGER_TWO_CYCLES))

From the file

%user%\mtw\mtb_shared\mtb-pdl-cat1\release-v3.2.0\devices\COMPONENT_CAT1A\include\psoc6_04_config.h

you can find all the enumerators for the interconnections where I got "TRIG_OUT_MUX_6_MDMA_TR_IN0" from. In this case, I have found this enumerator:

/* Trigger Output Group 6 - MDMA trigger multiplexer */
typedef enum
{
    TRIG_OUT_MUX_6_MDMA_TR_IN0      = 0x40000600u, /* cpuss.dmac_tr_in[0] */
    TRIG_OUT_MUX_6_MDMA_TR_IN1      = 0x40000601u /* cpuss.dmac_tr_in[1] */
} en_trig_output_mdma_t;

If you look at the trigger multiplexer block diagram you can find the DMAC in group 6, and the MUX has three kinds of triggers. The first is exactly the CPUSS.Zero, and in my case, I am using channel 0.

There you go, after enabling the DMAC you have to fire the software trigger and the DMA starts.

To recap here's the definition from Device Configurator:

#define cpuss_0_dmac_0_chan_0_HW DMAC
#define cpuss_0_dmac_0_chan_0_CHANNEL 0U
#define cpuss_0_dmac_0_chan_0_IRQ cpuss_interrupts_dmac_0_IRQn

cy_stc_dmac_descriptor_config_t cpuss_0_dmac_0_chan_0_Descriptor_0_config = 
{
    .retrigger = CY_DMAC_WAIT_FOR_REACT,
    .interruptType = CY_DMAC_1ELEMENT,
    .triggerOutType = CY_DMAC_1ELEMENT,
    .channelState = CY_DMAC_CHANNEL_ENABLED,
    .triggerInType = CY_DMAC_1ELEMENT,
    .dataPrefetch = false,
    .dataSize = CY_DMAC_BYTE,
    .srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
    .dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
    .descriptorType = CY_DMAC_MEMORY_COPY,
    .srcAddress = NULL,
    .dstAddress = NULL,
    .srcXincrement = 1,
    .dstXincrement = 1,
    .xCount = 16,
    .srcYincrement = 1,
    .dstYincrement = 1,
    .yCount = 1,
    .nextDescriptor = NULL,
};
cy_stc_dmac_descriptor_t cpuss_0_dmac_0_chan_0_Descriptor_0 = 
{
    .ctl = 0UL,
    .src = 0UL,
    .dst = 0UL,
    .xSize = 0UL,
    .xIncr = 0UL,
    .ySize = 0UL,
    .yIncr = 0UL,
    .nextPtr = 0UL,
};
cy_stc_dmac_channel_config_t cpuss_0_dmac_0_chan_0_channelConfig = 
{
    .descriptor = &cpuss_0_dmac_0_chan_0_Descriptor_0,
    .priority = 3,
    .enable = false,
    .bufferable = false,
};

And the code:

    #define scanline_dma_HW             cpuss_0_dmac_0_chan_0_HW
    #define scanline_dma_descriptor     cpuss_0_dmac_0_chan_0_Descriptor_0
    #define scanline_dma_descriptor_cfg cpuss_0_dmac_0_chan_0_Descriptor_0_config
    #define scanline_dma_CH             cpuss_0_dmac_0_chan_0_CHANNEL
    #define scanline_dma_CH_cfg         cpuss_0_dmac_0_chan_0_channelConfig
    
    char src[32];
    char dst[32];
    
    Cy_DMAC_Descriptor_Init(&scanline_dma_descriptor, &scanline_dma_descriptor_cfg);

    Cy_DMAC_Descriptor_SetSrcAddress(&scanline_dma_descriptor, (&src[0]));

    Cy_DMAC_Descriptor_SetDstAddress(&scanline_dma_descriptor, (&dst[0]));

    Cy_DMAC_Channel_Init(scanline_dma_HW, scanline_dma_CH, &scanline_dma_CH_cfg);

    Cy_DMAC_Channel_SetDescriptor(scanline_dma_HW, scanline_dma_CH, &scanline_dma_descriptor);

    Cy_DMAC_Channel_Enable(scanline_dma_HW, scanline_dma_CH);

    Cy_DMAC_Enable(scanline_dma_HW);

    if (CY_TRIGMUX_SUCCESS != Cy_TrigMux_SwTrigger(TRIG_OUT_MUX_6_MDMA_TR_IN0, CY_TRIGGER_TWO_CYCLES))

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Fri, 17 Mar 2023 11:13:40 GMT

I am working on a Dual-core project, in the CM0+ part.

    Cy_DMAC_Descriptor_Init(&scanline_dma_descriptor,
                            &scanline_dma_descriptor_cfg);

    Cy_DMAC_Descriptor_SetSrcAddress(&scanline_dma_descriptor,
                                     (void*)(&src[0]));

    Cy_DMAC_Descriptor_SetDstAddress(&scanline_dma_descriptor,
                                     (void*)(&dst[0]));

    Cy_DMAC_Channel_Init(scanline_dma_HW,
                         scanline_dma_CH,
                         &scanline_dma_CH_cfg);

    Cy_DMAC_Channel_SetDescriptor(scanline_dma_HW,
                                  scanline_dma_CH,
                                  &scanline_dma_descriptor);

    Cy_DMAC_Channel_Enable(scanline_dma_HW,
                          scanline_dma_CH);

    Cy_DMAC_Enable(scanline_dma_HW);

#define scanline_dma_HW             cpuss_0_dmac_0_chan_0_HW
#define scanline_dma_descriptor     cpuss_0_dmac_0_chan_0_Descriptor_0
#define scanline_dma_descriptor_cfg cpuss_0_dmac_0_chan_0_Descriptor_0_config
#define scanline_dma_CH             cpuss_0_dmac_0_chan_0_CHANNEL
#define scanline_dma_CH_cfg         cpuss_0_dmac_0_chan_0_channelConfig

Basically here, for test purposes, I am trying to perform a memory-to-memory copy. So I only need a simple software trigger.

The two buffers are simple arrays of chars:

char src[32];
char dst[32];

While the descriptor has been defined in Device Configurator:

#define cpuss_0_dmac_0_chan_0_HW DMAC
#define cpuss_0_dmac_0_chan_0_CHANNEL 0U
#define cpuss_0_dmac_0_chan_0_IRQ cpuss_interrupts_dmac_0_IRQn

cy_stc_dmac_descriptor_config_t cpuss_0_dmac_0_chan_0_Descriptor_0_config = 
{
    .retrigger = CY_DMAC_RETRIG_IM,
    .interruptType = CY_DMAC_DESCR,
    .triggerOutType = CY_DMAC_DESCR,
    .channelState = CY_DMAC_CHANNEL_ENABLED,
    .triggerInType = CY_DMAC_DESCR,
    .dataPrefetch = false,
    .dataSize = CY_DMAC_BYTE,
    .srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
    .dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
    .descriptorType = CY_DMAC_MEMORY_COPY,
    .srcAddress = NULL,
    .dstAddress = NULL,
    .srcXincrement = 1,
    .dstXincrement = 1,
    .xCount = 16,
    .srcYincrement = 1,
    .dstYincrement = 1,
    .yCount = 1,
    .nextDescriptor = NULL,
};
cy_stc_dmac_descriptor_t cpuss_0_dmac_0_chan_0_Descriptor_0 = 
{
    .ctl = 0UL,
    .src = 0UL,
    .dst = 0UL,
    .xSize = 0UL,
    .xIncr = 0UL,
    .ySize = 0UL,
    .yIncr = 0UL,
    .nextPtr = 0UL,
};
cy_stc_dmac_channel_config_t cpuss_0_dmac_0_chan_0_channelConfig = 
{
    .descriptor = &cpuss_0_dmac_0_chan_0_Descriptor_0,
    .priority = 3,
    .enable = false,
    .bufferable = false,
};

In the few examples I have found in Application Notes, and PDL documentation, the DMA transfer should start as soon as a "Cy_DMAC_Enable" it's invoked. Maybe I am wrong...

In the Trigger multiplexer diagram, I saw that the CPUSS.Zero should be a software trigger connected to the DMAC block, but I wasn't able to find what this "Zero" means in the CPU SubSystem.

RE: CY8C62 DMA from buffer to GPIO P10_0..2

misaz — Fri, 17 Mar 2023 10:29:39 GMT

In my app I use DW instead of DMAC and DW works. I will write several blogs about it. How do you trigger DMA(C) transfer?

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Fri, 17 Mar 2023 10:02:19 GMT

Definitely, there is something wrong with DMA. Currently, I did a simple test with a memory-to-memory transfer, like the one shown in the online PDL documentation, but it doesn't start at all. So there's something I am missing.

RE: CY8C62 DMA from buffer to GPIO P10_0..2

Digimorf — Thu, 16 Mar 2023 00:01:14 GMT

I forgot, If I send data to GPIO port by hand the output works, so I believe the problem is not in the address of the port.

scanline_rgb_port->OUT = pix;

RE: how to include 'cy_retarget_io.h' into our project?

Sudeep AJ — Tue, 14 Mar 2023 02:07:16 GMT

Thank you very much for the help!

how to include 'cy_retarget_io.h' into our project?

Sudeep AJ — Mon, 13 Mar 2023 20:09:07 GMT

So currently I am experimenting with HAL UART APIs and I learnt that there is cy_tetarget_io which helps us to use printf function with UART. I used it with the example project provided and it worked perfectly. But when I tried to include it in my Empty Project I am getting an fatal error. Can anyone please help me with this issue?

RE: how to include 'cy_retarget_io.h' into our project?

misaz — Mon, 13 Mar 2023 21:41:33 GMT

Here it is with picture. At first you need to select project to include library. Open any source file in the project. Remember than in case of dual core app there are two projects. Select project in which you want to use printf. Then open Library Manager as indicated in previous post:

Then click Add Library button:

Then mark retarget-io in Peripherals section and confirm by OK.

Then confirm Previous dialog by Update button.

RE: how to include 'cy_retarget_io.h' into our project?

misaz — Mon, 13 Mar 2023 21:13:29 GMT

You need to open Library Manager tool and include (mark checkbox) retarget_io library to your project. In demo project it is included but in some templates (for example empty project) it is not included by default.

RE: Is anyone using PSoC creator to build projects?

skruglewicz — Sun, 12 Mar 2023 19:47:31 GMT

I prefer modustoolbox over PSoC creator.. I used PSoC creator on windows for a PSoC 4 evk that was used in a project on hackster.io. It was ok and a little quirky with kitprog3..

Is anyone using PSoC creator to build projects?

Sudeep AJ — Sat, 11 Mar 2023 09:51:43 GMT

If it can be used could anyone please tell me which Device to select in the PSoC creator?

This is the first time exposure for me to work with something like this and I am taking time to learn and get comfortable using the IDEs before jumping into my project. I tried running example codes with Modus Toolbox but I feel I need to understand the code, but I am not able to find any documents explaining the code completely, if anyone could help me with this I would appreciate that.

RE: Is anyone using PSoC creator to build projects?

dougw — Sun, 12 Mar 2023 16:06:28 GMT

Modus Toolbox looks great and it also runs on Linux. The reason I still use Creator is simply that I am so familiar with it. They both do a huge amount of work for the developer.

RE: Is anyone using PSoC creator to build projects?

Jan Cumps — Sun, 12 Mar 2023 14:26:21 GMT

dougw , what's your verdict after using both for a while? I prefer Modus Toolbox.

RE: Is anyone using PSoC creator to build projects?

bidrohini — Sun, 12 Mar 2023 13:41:24 GMT

There are several resources that may be helpful. You can refer to the documentation and user guides provided by Infenion. www.infineon.com/.../

RE: Is anyone using PSoC creator to build projects?

dougw — Sat, 11 Mar 2023 17:23:20 GMT

I still use PSoC Creator for products it supports, but as misaz indicates it doesn't support all the new products.