Preface
In this design challenge, due to generosity of our sponsors: Cornel Dubilier and Element14, we had a chance of experimenting with supercapacitors of various families manufactured by CDE. Those included:
 six parts (of three different capacitance values) from DGH family (standard, highcurrent, 2.7V rated EDLC),
 six parts (of three different capacitance values) from DSF family (increased voltage, highcurrent, 3V rated EDLC),
 four parts (of two different capacitance values) from EDC family (lowcurrent, memory backup oriented, coincell type, 3.6V or 5.5V rated EDLC modules),
 four parts (of two different capacitance values) from EDS family (lowcurrent, memory backup oriented, coincell type, extended temperature range [+85 ºC], 5.5V rated EDLC modules),
 four parts (of two different capacitance values) from VMF family (extended maximum temperature range [+85 ºC], 3.8V rated LIC hybrid capacitors),
 two parts from VPF family (extended minimum temperature range [25 ºC], 3.8V rated LIC hybrid capacitors),
More information can be found in my first extra blog part.
Theory of supercapacitor
Standard capacitor model
Standard capacitor can be modeled as an equivalent circuit like below
where, in addition to expected C component there are:
 parasitic impedance of L that can change component's high frequency behavior, creating resonance potential and increasing impedance,
 Equivalent Series Resistance  ideal capacitor should have zero ESR, but in real world all capacitor elements have also some resistance that can increase power loss (and heat generation) inside of component  thus limiting it's lifetime  and impede capacitor's ability to transfer charge. It can be further divided into (more commonly used) AC ESR  calculated for AC current of given frequency, and DC ESR that affects capacitor role as power source  this parameter is, in fact, direct current internal resistance the capacitor,
 and Rleak  internal resistance between electrodes that is discharging capacitor when left without power,
Supercapacitor
Supercapacitors, also known as doublelayer capacitors (EDLC), due to their unique construction that gives them very large effective electrode surface with very thin separation, can have capacitances far surpassing other constructions (which is directly related to the fact that capacitance is defined as ε*S/d, that is  it is directly proportional to electrode surface area and inverse proportional to the distance between electrodes).
They also have unique operational characteristics that should be taken into consideration when designing circuits that contain them. In opposition to the typical capacitor, supercapacitor is modeled as the circuit as below
As can be seen, supercap, in addition to leakage resistance, is modeled as many (maybe infinite) number of serial RC circuits connected in parallel, with increasing serial resistances.
This model raises several questions about actual parameters of that capacitor:
 what is measured as nominal capacitance? Sum of all capacitances? Only C1? How much capacitance  if any  is left from this measurement?
 what is considered an ESR(DC) value of the component? Again  only R1?
Additional observation worth noting is the fact that selfdischarge current can be reliably measured only after all the capacitance gets charged, otherwise process of charge migration from lowresistance parts of capacitor to other areas could be easily confused with higher than expected selfdischarge current. Documentation from manufacturers advise charging periods in the range of 72100h before leakage current measuring.
Measurement methods
To try to answer those questions a number of measurement methods were researched and selected. They are presented below, but first let's begin from some theory.
An equation describing process of charging a capacitor through serial resistance is as following:
U = U_{0} (1  exp( t/RC))
and for discharging:
U = U_{0}exp(t/RC)
where point where t/RC equals 1 is known as time constant of RC circuit and written as τ (tau).
When time equals τ, exp(t/RC) becomes 0.3679, which gives us the simplest way of measuring capacitance.
Time to voltage threshold
This method is based of counting time to obtain threshold voltage (0.632 of power supply voltage when charging and 0.368 of initial voltage during discharge). When this voltage is detected, we can assume that τ (or RC) has passed, so when R is known C is easy to obtain. This method needs fast sampling and good precision of both time and voltage measurement.
Voltage change in time
More advanced method is allowing for some variations both in time and voltage range.
RC = (t_{2}  t_{1})/log(1  U_{2}/U_{0})
In this case, actual voltage and timestamps can be used, allowing for compensation of some measurement issues  for example, when precise threshold voltage was not sampled.
Charging curve approximation
When measurement data is noisy or samples are obtained from points far away from threshold lines, specialized match software can be used to approximate sample vector using theoretical curve with unknown parameters. This way, when fitting error is sufficiently small, capacitance can be calculated from approximated parameters of charging curve.
Capacitor charge calculation
Another way of measuring capacitance is to sum (integrate) input current curve. This way component capacitance can be measured even if charging curve for some reason is not exactly fitting equation known from capacitor theory. In this case capacitance can be calculated from the following formula:
C=Q/U
where Q is capacitor's charge and U is voltage obtained during charging.
Measurement setup
As a base for experiments, Arduino Uno board was selected  mainly because of it's integration potential with opensource math package, GNU Octave. Actually, Lattepanda v.1 SBC was used, but with external Arduino Uno instead of builtin Arduino Leonardo as measurement module (to protect SBC from accidental damage).
More details were included in my third extra blog.
Measurement unit schematics is very simple:
Relay shown on schematics is in fact Arduino relay module  complete with driver and protection diode.
As a CV/CC PSU, inexpensive downconverting switching power supply module was used  like this one https://www.electroschematics.com/dcmodule/
It was initially setup to provide about 2V with current limit of 200mA.
Initial test were conducted on typical 1500uF electrolytic capacitor. My fifth extra blog validates this setup and explains that by using curve fitting one can enhance measurement quality (even in the case of sparse measurements)
Meter operation was validated using 1500uF electrolytic capacitor, providing similar and repeatable readings using first three methods, like below:
run at 1694602171 timestamp
Capacitance [charge, using coarse charge time] = 0.001690 [F]
Capacitance [charge, using precise charge time] = 0.001692 [F]
Capacitance [charge, using curve fitting] = 0.001668 [F] at estimated supply voltage of 2.164570 [V]
Capacitance [discharge, using coarse discharge time] = 0.001680 [F]
Capacitance [discharge, using precise discharge time] = 0.001682 [F]
Capacitance [discharge, using curve fitting] = 0.001688 [F] at estimated supply voltage of 1.996706 [V]
charge/discharge difference [coarse time] = 0.597245 [%]
charge/discharge difference [precise time] = 0.612634 [%]
charge/discharge difference [curve fitting] = 1.172711 [%]
end of run at 1694602171 timestamp
run at 1694605392 timestamp
Capacitance [charge, using coarse charge time] = 0.001699 [F]
Capacitance [charge, using precise charge time] = 0.001718 [F]
Capacitance [charge, using curve fitting] = 0.001670 [F] at estimated supply voltage of 2.162593 [V]
Capacitance [discharge, using coarse discharge time] = 0.001666 [F]
Capacitance [discharge, using precise discharge time] = 0.001672 [F]
Capacitance [discharge, using curve fitting] = 0.001690 [F] at estimated supply voltage of 1.995041 [V]
charge/discharge difference [coarse time] = 1.917687 [%]
charge/discharge difference [precise time] = 2.650012 [%]
charge/discharge difference [curve fitting] = 1.168563 [%]
end of run at 1694605392 timestamp
Also, curve fitting method delivers approximation very well fitting actual measurement data:
even test on sparse measurement data is providing adequate fit:
Old technology
As an example of supercapacitor (possible) evolution, some measurement of Panasonic Gold Capacitor (p/n EECRF0H105) were included. Those parts, maybe 20 years old, are of memory backup variety  that is, optimized for low leakage current and stacked together to form 5.5V battery.
Visibly bigger than current offering with comparable parameters from CDE, they have following parameters:
 voltage: 5.5V (which means that it is a supercapacitor battery, not a single cell),
 capacitance: 1F
 ESR_{DC}: about 40Ω
 tolerance: 20%/+80%
When installed in (DS1302 based) Arduino RTC module as below
{gallery}DS1302 module 

their leakage current was measured at:
Date 
Voltage 
Charge/discharge time  Calculated discharge current [uA] 
20210923 17:45 
3,97V 

20210924 10:07 
2,97V 
16:22:00 
16,97 
20210924 17:23 
4,01V 
07:16:00 

20210927 10:30 
4,25V 
65:07:00 

20210927 17:44 
4,27V 
07:14:00 

20210928 06:15 
3,82V 
12:31:00 
9,99 
20210930 02:06 
4,24V 
43:51:00 

20210930 11:10 
3,89V 
09:04:00 
10,72 
20211004 17:30 
4,37V 
102:20:00 

20211005 00:33 
4,25V 
07:03:00 
4,73 
20211005 06:03 
4,15V 
05:30:00 
5,05 
20211006 09:40 
3,85V 
27:37:00 
3,02 
20211007 23:48 
3,55V 
38:08:00 
2,19 
20211008 09:45 
3,48V 
09:57:00 
1,95 
20211010 02:38 
3,25V 
40:53:00 
1,56 
This data suggests that selfdischarge current of this capacitor needs several hundreds of hours of charging to stabilize at low level.
Current technology
Capacitance measurement
For capacitance measurement 1F/2.7V supercapacitor was selected. Initial measurements  for time range of 8*RC (widely assumed as time needed for fully charging a standard capacitor) and R=22Ω showed similar dis/charge curves:
So far  so good. But trying to add curve fitting data series showed that something is amiss:
Our approximated curves, precisely fitting measurement data when measuring electrolytic capacitor, are not following captured data when used with supercapacitor.
When investigating further, approximated curve has RC constant of 2.0655e+01, which means that capacitance would be 0.94F. In addition, charging voltage approximation was lowered from (measured) 2.19V to 2.084V.
When additional degree of freedom was introduced (variable initial voltage  supercapacitors are known to be difficult to both charge and fully discharge) by modifying fitting function into:
fc = @(p, x) p(3)+p(1)*(1exp(x / p(2)));
minimally better fit was obtained. In this plot one additional series was added  model charging curve of 1F capacitor (dark green top curve).
As we can see, better fit was obtained by artificially raising initial voltage to 0.18V and lowering power voltage to 1.94V.
Model curve for 1F capacitor charged to 2.19V is significantly different from obtained data. This difference can be explained by supercapacitor theoretical model, when some percent of total capacitance is connected through highresistance serial resistors, so it is difficult to charge but also to discharge (some manufacturer's data consider supercapacitor fully discharged when left shortcircuited for period in the range of tens of hours).
So  how to measure supercapacitor capacitance when we cannot use traditional equations? Either by using some sort of approximation (as suggested in manufacturer's documentation) or by counting the charge loaded when capacitor is charged (or charged and discharged  this way we will have a chance to eliminate leakage current from our measurement).
Measurement was repeated with time of 24RC and results are as below
It looks like that capacitor is still charging after 24*RC  measured charge during discharge phase is slightly bigger that in previous plot: 2.2714C vs 2.1411C (for 8RC time), so curve increase is not only caused by leakage current, but some of this energy gets stored.
Capacitance calculated by this method (given initial voltage during discharge of about 2V) is 1,.07F when charging for 8RC and 1.13F when charging for 24RC.
ESR measurement
In already mentioned by other challengers AVX datasheet, ESR_{DC }measurement using following procedure is proposed:
It is based on observation that ESR can be detected during load change  either during charging (when lowering charging current should cause reduction of voltage drop across an ESR, decreasing observed capacitor voltage) or during discharge  when load removal should cause voltage increase. In case of supercapacitor it seems problematic because of existence of high resistance areas  charge in those areas could migrate to partially depleted low resistance parts, increasing voltage more than only ESR effect would cause. But let's see what we can observe by experimenting.
Our capacitance meter was modified by removing discharge resistor and only enabling it briefly to cause voltage drop across the ESR.
This setup (when 4.7Ω discharge resistor is used to generate significant current) generates plot like this:
As can be seen, when load is applied, voltage across the capacitor drops shiftly and when load is removed it rebounds a little. So far, so good.
Now let's see what happens after load was disconnected:
it seems that voltage starts to rebound. When zooming into the area of rebound we can see:
it seems that voltage rebounds to certain level and stays this was  no sign of excessive charge transfers (that probably would be visible as constantly increasing voltage curve)  which validates proposed measurement technique (especially when wait time is short  like 2s).
In this case maximum ESR (in absence of other effects) can be calculated from load current and visible voltage drop:
Current is in the range of 1.63V/4.7Ω=0.347A and apparent voltage drop is about 60mV, giving ESR of about 170mΩ (that is below maximum ESR specified in the datasheet as 400mΩ).
Leakage current measurement
Leakage current measurement was conducted using voltage measurement across 1kΩ serial resistor when charging, after > 100h of continuous charging (this way we can measure current constantly taken by  hopefully  fully charged capacitor, in other words  leakage current). This is alternative method to measuring voltage decrease of disconnected capacitor and calculating leakage from voltage drop over time.
Capacitor type  precharged > 100h  without precharging 
1F/2.7V  1.7uA  62uA 
5F/2.7V  2.7uA  80uA 
10F/2.7V  3.2uA  90uA 
3F/3V  4uA  90uA 
7F/3V  4.6uA  97uA 
25F/3  5.2uA  350uA 
0.22F/3.6V  1.4uA 
Two observations can be made  leakage current can be easily mistaken with low level charging current when highimpedance areas of partially charged capacitor are charged. And another one  that 3V family has slightly higher leakage current than 2.7V one.
Supercapacitor stacking
In some usecases, supercapacitors need to be grouped into the batteries to be usable  mainly because their low working voltage, making it difficult to extract all the stored energy of supercapacitor discharged to  for example  0.6V. To overcome this, serial connected batteries are being built, but here balancing problem appears. As explained with more details in my fourth blog, balancing techniques can be divided into three categories:
 statistical (when battery parameters are set to take into account worst possible individual components parameter mismatch),
 passive (when components are kept inside safe parameter ranges using resistors, diodes or MOSFETs),
 active (where opamps, converters or even charge pumps are employed to keep individual supercapacitors equally charged)
Active balancing can be expensive and complicated (which can mean  failure prone) and passive are usually low power (conducting currents in the range of milliamps).
Proposed voltage limiter
Basing on idea of highpower Zener diode as passive supercapacitor balancer (that could have steeper characteristic than MOSFET key binned to have gate threshold voltage in the range of capacitor's maximum voltage), following circuit was proposed.
Selected for this design TIP122 has builtin CE reverse diode (similar to MOSFET's), so voltage reversal protection is also provided.
Main obstacle in this case is to provide low enough threshold voltage with high current capacity and steep on/off curve. Both low voltage Zener diodes and LED diodes were considered as voltage reference and simulations were run.
PSpice simulated circuit's response is shown below:
To obtain curve like this, power supply with voltage greater than 3V was turned on for 20s, then turned off. Due to limited design time this circuit was not validated yet as physical module.
LIC charging module
With allowed voltage range of 2.2V  3.8V (and especially surge voltage of 4.2V) LIC hybrid supercapacitors from CDE look strikingly similar to standard LiIon cells.
In this paragraph, standard (and dirtcheap) LiIon charger module will be modified to charge (and protect from overdischarging) a LIC supercapacitor. Given 4.2V surge voltage of this part, there is a chance that unmodified TP4056 charger could be used, but given it's charging profile (shown below) and definition of surge voltage as absolute maximum, not to be maintained for the long time, (and published research that suggest that LIC electrode is going to be permanently damaged both by applying minimum and maximum voltage) circuit modification was proposed.
By adding one serial diode between TP4056 output and LIC supercapacitor and replacing current setting resistor (R3  usually scaled for 0.5A  1A current) with 20kΩ one (limiting charge current to about 50mA), we will obtain overdischarge protected charger with voltage limit of about 3.7V. Modification is as follows:
Trace between TP4056 and protection circuit needs to be cut and rectifier diode (selected as such to have large enough Vf and sufficient current) installed. Then, R3 should be desoldered and replaced:
to create a complete charger that can be seen on the photo below:
Summary
As there was shown during the experiments, supercapacitors are unique components, similar enough to standard capacitors to be treated as the same, but with enough differences in behavior to surprise a designer that is not paying enough attention. New constructions, like those provided by Cornell Dubilier, are getting better all the time, reducing known shortcomings and easing implementation.