/challenges-projects/design-challenges/path2programmable/b/blog/posts/week-1Introduction Lab 0 - Pr-requisite Problem of Xilinx JTAG + Serial [0700] HW Lab 1 - Inconsistent Folder Format HW Lab 2 - Tip for Mapping I/O Pins HW Lab 3 - Probably Missing a Step HW Lab 6 - Slightly Different Conclusion en-USTelligent Community 12