/challenges-projects/design-challenges/path2programmable/b/blog/posts/congrats-to-all-selected-traineesHope please add your experience and study materials so that it will help for not selected people to learn out of your experience.en-USTelligent Community 12https://community.element14.com/challenges-projects/design-challenges/path2programmable/b/blog/posts/congrats-to-all-selected-traineesSat, 19 Oct 2019 22:51:12 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f1faaa68-c93a-4808-8c93-1d6b7de4fd49cmelement140<p>I watched 22 videos and completed 6 labs so far. The training is great for me. It is designed for beginner or middle level users of Zynq UltraScale+ MPSoC. It focus on using the on-chip hardware PS and existing IP not on Verilog/VHDL-based FPGA design.</p><img src="https://community.element14.com/aggbug?PostID=7996&AppID=242&AppType=Weblog&ContentType=0" width="1" height="1">