/challenges-projects/design-challenges/path2programmable/b/blog/posts/developing-zynq-ultrascale-mpsoc-software-with-xilinx-sdk-lab-8In this lab you are advised not to share or archive your workspace simply by zipping it up and sending it off. In my FPGA designs at work the verilog designs are foten shared among two engineers while the software for the SOC FPGa desing is done by oen-USTelligent Community 12