<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Introduction to Zynq UltraScale+ MPSoC Hardware Lab 6</title><link>/challenges-projects/design-challenges/path2programmable/b/blog/posts/introduction-to-zynq-ultrascale-mpsoc-hardware-lab-6</link><description>In this lab the BRAM added from the previous lab is used to buffer data going between the PS and PL. A software application that enables the PS DMA engine was used to show the efficiency gains achieved by passing data between the PL-based BRAM ...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>