/challenges-projects/design-challenges/path2programmable/b/blog/posts/introduction-to-zynq-ultrascale-mpsoc-hardware-lab-8IP created is tested via simulation as well as in hardware. Embedded designs like Zynq MPSoC requires software to be written to test IP. The LogiCORE IP JTAG-AXI core was added in a previous last lab and the core was customized. It can generate AXI ten-USTelligent Community 12