<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Path to Programmable III Training Blog #04: My first Custom IP in Vivado</title><link>/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-04-my-first-custom-ip-in-vivado</link><description>The Vivado Design Suite provides an IP-centric design flow that helps us quickly turn designs and algorithms into reusable IPs. The Vivado IP catalog is a unified IP repository that provides the framework for the IP-centric design flow. This catalog </description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Path to Programmable III Training Blog #04: My first Custom IP in Vivado</title><link>https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-04-my-first-custom-ip-in-vivado</link><pubDate>Wed, 02 Oct 2024 05:23:09 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:215c1f24-6c75-44bb-acbc-b0e796674db8</guid><dc:creator>ftm_mrbs</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;[mention:af261df15baa4b9d85cfbb23b3e098e2:e9ed411860ed4f2ba0265705b8793d05]&amp;nbsp; Hi, great job. How did you assign 8 bits of leds to slv_reg with 32 bits?&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=26537&amp;AppID=395&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Path to Programmable III Training Blog #04: My first Custom IP in Vivado</title><link>https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-04-my-first-custom-ip-in-vivado</link><pubDate>Sat, 22 Jul 2023 10:03:59 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:215c1f24-6c75-44bb-acbc-b0e796674db8</guid><dc:creator>javagoza</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;Hi&amp;nbsp;[mention:5a1cfe9081a4403c8a680a2b4d1abcfe:e9ed411860ed4f2ba0265705b8793d05]&amp;nbsp;great job.&amp;nbsp;I think you only need&amp;nbsp;to add&amp;nbsp;the user logic part of the AXI Lite wrapper&lt;/p&gt;
&lt;p&gt;// Add user logic here&lt;/p&gt;
&lt;p&gt;// User logic ends&lt;/p&gt;
&lt;p&gt;I have a complete example of the whole process, also done in Verilog, including drivers for Vitis in the following blog&lt;/p&gt;
&lt;p&gt;&amp;nbsp;[mention:383873595f344fad89b1f2a7a0c24135:f7d226abd59f475c9d224a79e3f0ec07]&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I hope you find it useful.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=26537&amp;AppID=395&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>