/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socXilinx ZYNQ-7000 AP SoC consists of a Programmable Logic (PL)(FPGA) and Processing Subsystem(PS) (ARM Cortex-A9). The communication logic/interface between the PL and PS is an essential component of ZYNQ Architecture for data transfer. The AXI Intercen-USTelligent Community 12https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socMon, 15 Sep 2025 10:44:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f8918f5e-66fa-48ff-943f-f1f31b666ac2bit2silicon0<p>[View:https://drive.google.com/file/d/1Ed5b_znqlt9Pm8QcdBZkO-pTd9WI63Jp/view?usp=sharing:640:50]</p> <p>PL LED not glowing when running from Vitis<br />My PL LED glows when I program the bitstream directly through Vivado Hardware Manager. But when I run an application from Vitis, the PS programs fine but the PL seems to get cleared and the LED no longer glows, even though the hardware platform was generated with the bitstream (XSA). Any idea why PL isn&rsquo;t staying programmed when running from Vitis?</p> <p>[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:240e68a3-07ed-428b-85bb-c262b418ae6e:type=text&text=Verilog%20PL%20code%0A%60timescale%201ns%20%2F%201ps%0A%0Amodule%20adder%28%0A%20%20%20%20input%20%5B31%3A0%5D%20in1%2C%0A%20%20%20%20input%20%5B31%3A0%5D%20in2%2C%0A%20%20%20%20output%20%5B31%3A0%5D%20sum%2C%0A%20%20%20%20output%20ledout%0A%29%3B%0A%20%20%20%20assign%20sum%20%3D%20in1%20%2B%20in2%3B%0A%20%20%20%20assign%20ledout%20%3D%20sum%5B0%5D%3B%0Aendmodule%0A%0A%0AConstraint%20file%0Aset_property%20PACKAGE_PIN%20W21%20%5Bget_ports%20ledout%5D%0Aset_property%20IOSTANDARD%20LVCMOS18%20%5Bget_ports%20ledout%5D%0A%0A%0AVitis%20C%20code%0A%23include%20%22xparameters.h%22%0A%23include%20%22xgpio.h%22%0A%23include%20%22xil_io.h%22%0A%23include%20%3Cstdio.h%3E%0A%0Aint%20main%28%29%20%7B%0A%20%20%20%20Xil_Out32%28XPAR_AXI_GPIO_0_BASEADDR%2C%202%29%3B%20%20%20%2F%2F%20Write%20to%20register%20A%0A%20%20%20%20Xil_Out32%28XPAR_AXI_GPIO_1_BASEADDR%2C%202%29%3B%20%20%20%2F%2F%20Write%20to%20register%20B%0A%20%20%20%20int%20result%20%3D%20Xil_In32%28XPAR_AXI_GPIO_2_BASEADDR%29%3B%20%2F%2F%20Read%20SUM%0A%20%20%20%20xil_printf%28%22Result%20%3D%20%25d%5Cr%5Cn%22%2C%20result%29%3B%0A%20%20%20%20%0A%20%20%20%20return%200%3B%0A%7D]<br />I had attached my PL code with constraints, PS code, and also attaching my block diagram</p> <p><br />Thank you</p><img src="https://community.element14.com/aggbug?PostID=26539&AppID=395&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socFri, 07 Feb 2025 13:56:25 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f8918f5e-66fa-48ff-943f-f1f31b666ac2SAKSHI211<p>heyy! i am having issues with generating bit stream file would u pls help!</p><img src="https://community.element14.com/aggbug?PostID=26539&AppID=395&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socThu, 16 May 2024 09:19:45 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f8918f5e-66fa-48ff-943f-f1f31b666ac2rohini1<p>Can we program the PS in Python instead of C?</p><img src="https://community.element14.com/aggbug?PostID=26539&AppID=395&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socSun, 23 Jul 2023 13:44:14 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f8918f5e-66fa-48ff-943f-f1f31b666ac2prashanthgn.engineer0<p>Nice Blog :&nbsp;&nbsp;[mention:5a1cfe9081a4403c8a680a2b4d1abcfe:e9ed411860ed4f2ba0265705b8793d05]&nbsp;&nbsp;</p><img src="https://community.element14.com/aggbug?PostID=26539&AppID=395&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/challenges-projects/design-challenges/pathprogrammable3/b/blog/posts/path-to-programmable-iii-training-blog-05-inter-communication-between-ps-and-pl-of-zynq-socSun, 23 Jul 2023 05:06:16 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f8918f5e-66fa-48ff-943f-f1f31b666ac2navadeepganeshu1<p>Good one.</p> <p>Shouldn&#39;t this work just from the Vivado implementation if you upload the .bit file? I couldn&#39;t understand what is being done in the Vitis application project.</p><img src="https://community.element14.com/aggbug?PostID=26539&AppID=395&AppType=Weblog&ContentType=0" width="1" height="1">