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RE: In zturn board usb otg to access pendrive to see the result console window by using uart

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RE: Path to Programmable - Blog 10 - Video Project

siampakos — Tue, 19 Nov 2024 09:22:09 GMT

Can you please provide me the code for this example you used? The zedboard.org site is down and there is no way for me to find it. I need to use the pmod camera module for an application in eclypse z7 board.

RE: Software Application Development for Minized Board in Xilinx SDK

Michelleantonio — Thu, 19 Sep 2024 15:02:37 GMT

I've recently started working on software application development for a Minized board using the Xilinx SDK, and it's been quite the experience! The step-by-step process of importing the hardware definition file and configuring the board support package was really insightful. If anyone else is dabbling in this, be sure to check out the detailed guides available online. Also, if you need a mobile app development company near me, there are some great local options that can help you with your tech projects!

RE: In zturn board usb otg to access pendrive to see the result console window by using uart

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RE: Software Application Development for Minized Board in Xilinx SDK

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RE: Working with DMA through AXI between DDR and PL BlockRAM

prasad.kumawat.22 — Wed, 03 Feb 2021 09:25:09 GMT

Hi, [mention:390bd829517d47b8b6a57a2c29a935f1:e9ed411860ed4f2ba0265705b8793d05] I saw in most of the images that you are importing examples from a folder called "Speedway/ZynqHW/ZynqDesign." Will you please let me where I can get the source or can you please direct me on how will be able to get the direction to those lab exercises.

RE: SW Application Development - Hello World with UART on Minized Board

reza20 — Fri, 26 Jun 2020 15:56:52 GMT

Side tracks from main issue.

RE: Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA

kriswil — Fri, 24 Apr 2020 19:05:35 GMT

Does anyone know a tutorial on how to use PL DMA for streaming data from PL IO straight to DDR using PL DMA (which is much faster than PS DMA) ? I've been trying to find for a while. There are some examples, like the one for Zybo but it has custom lock IP Cores which I can't access.They're using AXI Video In / Video Out for HDMI video signal. I'm looking to stream raw video data directly from a video CMOS chip, not HDMI format.

So it would look like this:

input : PL IOs -> (something - either IP Core or Verilog code) -> PL DMA -> AXI -> PS -> DDR3

I can't figure out how to send data from custom PL Block (IP Core or Verilog) to PL DMA.

Then I need to stream it out from DDR3 to Ethernet:

DDR3 -> PS -> Ethernet+DMA : output

Anyone seen any tutorial like that?

Thank you!

RE: Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA

kriswil — Fri, 24 Apr 2020 16:09:34 GMT

Hello. I love the blog. It's very useful! One question: where can I find those videos? Like for example: HW Chapter 7 video: Zynq PS DMA Controller.

There is no screen shots of how to configure DMA. I assume that's in the video?

RE: 06 - "The Projekt"

clem57 — Mon, 11 Nov 2019 14:22:17 GMT

Sometimes the journey is more important than the destination. In this case, what a journey [mention:5e0d047951674ffa9aa9eee6844fb3ef:e9ed411860ed4f2ba0265705b8793d05] .[View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-85f43e1c-3bb1-4ba4-9267-dad5e8b931e3/contentimage_5F00_3.png:16:16]

RE: Summary of Module 2 Path to Programmable ZYNQ SW blogs

qcarver — Tue, 08 Oct 2019 14:45:47 GMT

S Nidhi,

Thank you for these posts. I wonder if you can help me.

I too am doing the "ALl Programmable SoC Software Lab" with my MiniZed 72007-G.

I found the labs from the Vendor here

However, this is the 2016 version and even though the page says it will work for MniZed, there is no MiniZed directory in the ZynqDesign directory (only for microzed, picozed and zedboard).

I see you have a 2018 version of tlhe labs which includes the .hdf file for miniZed. Can you tell me where you got your labs from, or atleast where I can find the hdf file?

Thank You,

RE: Working with DMA through AXI between DDR and PL BlockRAM

14rhb — Sun, 29 Sep 2019 08:28:56 GMT

Hi [mention:390bd829517d47b8b6a57a2c29a935f1:e9ed411860ed4f2ba0265705b8793d05] I noticed your post when you published it and bookmarked it for later reading....and sorry I then forgot. I'm currently working on my Z7k Logic Analyser: Progress Update #2 and I am now finding your post very interesting and useful. Thank you for the great explanation of these building blocks, BRAM, DMA and the AXI.

RE: SW Application Development - Hello World with UART on Minized Board

clem57 — Sat, 24 Aug 2019 10:44:21 GMT

[mention:390bd829517d47b8b6a57a2c29a935f1:e9ed411860ed4f2ba0265705b8793d05] Great job. Look forward to your next project.

RE: SW Application Development - Hello World with UART on Minized Board

gearhead — Fri, 23 Aug 2019 15:27:05 GMT

I just watched your video yesterday. Yes, I also learned a few new things that help my understanding. I have been doing exercises for several months and slowly getting comfortable with the Vivado tools and SoC design methodology.

I have a MicroZed board and it has taken longer than I though to move into my own design vs. just working tutorials.

I have spent many years using the Xilinx ISE tool for FPGA development up to Virtex-4 chips, so there is a lot to learn with SoC development.

Thanks, Steve

RE: Path to Programmable Blog 4 - Adding a PL Peripheral & using PS DMA

davmaz — Wed, 22 May 2019 14:33:29 GMT

Very nice tutorial! Thank you.

However I am continually frustrated trying to get a DMA driver running (ZCU111 -> Ubuntu 16.04). Xilinx code seems to be broken.

Do you have, or could you point me to, code that 'really' works?