RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

shabaz — Sat, 27 Oct 2018 11:39:02 GMT

Text Zoom for Xilinx Document Navigator on Windows 10

I might add this to a Xilinx Tips or Practices blog post or something if I come across more of these, but basically to document it somewhere for now at least..

Vivado comes with a lot of documentation, and I'm still exploring it. The documentation navigator, called Xilinx Document Navigator or DocNav, looks comprehensive, but is hard to view, because the text is tiny (smaller than a millimetre in height).

It looks like this (the usual text size in the background is much larger for comparison):

[View:/resized-image/__size/717x407/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/0572.contentimage_5F00_188995.png:717:407]

This was the only solution I could find:

Find or type DocNav from the Windows search bar, and right-click and choose Open file location. That will show where the Windows Shortcut for the application resides, in the file manager.

Next, click-through as shown in the highlighted areas below:

[View:/resized-image/__size/620x487/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/8311.contentimage_5F00_188996.png:620:487]

The end result is a more usable text size!

[View:/resized-image/__size/715x414/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/0871.contentimage_5F00_188997.png:715:414]

RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

snidhi — Wed, 24 Oct 2018 07:58:25 GMT

[mention:b0bc65b9ecdc4307bd967592f00e340a:e9ed411860ed4f2ba0265705b8793d05] In the further labs 3 4 5 there is not the main focus on the floor planning. I did by myself for learning and playing around with Vivado.

I was just clicking here and there [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/contentimage_5F00_403.png:16:16]

Cheers

RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

shabaz — Wed, 24 Oct 2018 00:33:36 GMT

Hi [mention:87db22544d8844169f5ec3635dfac969:e9ed411860ed4f2ba0265705b8793d05]

(Replying here otherwise it gets too indented, and there will be some diagrams in this comment):

This is great to hear that you’re up to the Hello World stage. I totally agree, some of it is still ‘magic numbers’, but I think the trainers took the approach that it is better to put some detail aside for now, on the understanding that it may later make more sense, otherwise it could take a very long time to get to the stage of executing a program on the Zynq. I don’t actually mind that in some cases, it is an approach I’ve seen a few times, sometimes needed when there is too much detail to absorb otherwise. There are maybe more than 10k pages on the Zynq across many guides/manuals, so that detail is a little scary to me currently. It reminds me of my first job in a field that I was not familiar with at the time, where the standards the product were based on were 3GPP defined, and as a result ran to hundreds of thousands of pages, and for a few weeks I was prepared to ignore the heavy detail and just assume that what I was working on made some sense to the bigger picture, but then I felt frustrated, knowing that there were many unknowns, and not knowing for sure if I was delving into the correct documents (amongst thousands) or not. Even after several years I just had a vague idea, but in the end enough to be confident in my area. But you’re right, it is good to dig into this area now, since otherwise it can get too abstract… so here goes : )

Regarding the UART pins and the reason for them being allocated MIO 48..49, my understanding currently is that this is due to the Zynq chip bringing out some pins directly from the Processor System, and so if no programmable logic is being used then like other ARM chips, the connections for certain I/O peripherals (IOP) like UART, I2C, I2S etc., can only come out in certain combinations, and cannot be brought out on any arbitrary pin. So, the Vivado GUI lists the valid options, and if (say) MIO 48..49 are selected for UART, then those pins are now not available for other peripherals that may have been allowed to use those pins too.

The way the Processing System is implemented, the user has a choice to either connect to it from the outside world on the dedicated MIO (Multiplexed I/O) pins (and in that case only certain combinations are possible), or the user can route the peripherals (UART, I2C etc) into the programmable logic area, using some internal connections called EMIO (Extended Multiplexed I/O). If EMIO is used, then the programmable logic has access to those connections and then the connections can be routed to any pin the programmable logic can be wired to.

This is explained in a Xilinx MIO and EMIO video where they use this diagram to explain it:

[View:/resized-image/__size/756x380/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/1805.contentimage_5F00_188988.png:756:380]

Although Vivado will automatically list the available MIO options for each peripheral, there is a table (table 2-4) buried in the 2000-page Zynq Technical Reference Manual PDF doc

that shows the valid combinations:

[View:/resized-image/__size/830x854/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/6747.contentimage_5F00_188989.png:830:854]

Only the blue shaded cells are valid for the particular Zynq chip IC package that is used on the MiniZed board (the other cells are valid for the larger packages). According to that table, the UART1 is valid on MIO pins 8..9, 12..13, 28..29, 32..33, 36..37, 48..49 and 52..52, and this matches the options in the drop-down when configuring in Vivado.

The actual physical pin on the chip mapping is in a table available for the Zynq device/package, downloadable as a text or CSV file here: https://www.xilinx.com/support/package-pinout-files/zynq7000-pkgs.html

[View:/resized-image/__size/512x308/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/8322.contentimage_5F00_188990.png:512:308]

For the chip used on the MiniZed, this is the direct link: https://www.xilinx.com/support/packagefiles/z7packages/xc7z007sclg225pkg.txt

So from there, searching for MIO48 and MIO49 shows these are BGA pins B12 and D13 respectively. The diagram is in the Zynq-7000 Packing Specification PDF in Figure 3-1.

The empty unfilled diamonds are the MIO pins.

[View:/resized-image/__size/988x392/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/6278.contentimage_5F00_188991.png:988:392]

I’ve yet to fully see how to explore all this in Vivado (and hopefully the training will provide that soon, because in later labs, according to [mention:b2133293ca8847a49f3e49ff4d9bd9bf:e9ed411860ed4f2ba0265705b8793d05] blog Week 3: Done!! Lab3 Lab4 and Lab5 the floorplan stuff is explored further). Anyway, from some limited exploration I was able to see the pins in Vivado, but currently I don’t know how use this part of the GUI:

[View:/resized-image/__size/862x855/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/7840.contentimage_5F00_188992.png:862:855]

As you say, this is reflected in the MiniZed schematic at the MiniZed documentation site :

[View:/resized-image/__size/778x572/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/5706.contentimage_5F00_188993.png:778:572]

Regarding the training material, I'm still exploring it, but it's good so far.

It consists of PDF lab guides, this is an example snippet from lab 2:

[View:/resized-image/__size/790x410/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-232af0b4-ec4f-477e-b775-279289fc4000/7824.contentimage_5F00_188994.png:790:410]

Everything is clean and easy to follow and they refer off for additional reading/experiments in places.

There are exercises and solutions too, reference material, and lots of videos covering hardware and software. The overall bundle of files is massive.

The video/audio quality is very good as is the material they present.

I am still exploring it so i don't have full conclusions on that currently, but so far I think it is very good material, very different from old-school training courses which supply aged black-and-white faded PDF powerpoint printouts in binders : ) I've seen a few of those in the past.. : (

Anyway, I think it is really great you're willing to explore all this, given that it's definitely a non-trivial exercise to bring up any ARM applications processor from scratch, let along inside a chip with programmable logic. I think people spend weeks doing that with just the processor alone : ) so the training definitely moves fast in this area..

RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

DAB — Tue, 23 Oct 2018 19:46:20 GMT

Very good update.

I agree, the Vivado software appears to be very powerful and aimed at getting a novice user up to speed quickly.

That said, it was a canned exercise and I expect everything to be included.

We will see how well you do when you try to build a new capability from scratch.

DAB

RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

genebren — Tue, 23 Oct 2018 18:35:01 GMT

Great blog on your progress down the path! Good luck on your continued journey.

Gene

RE: Xilinx ZYNQ - Blog 2 - Getting Code Running on the SoC

Fred27 — Tue, 23 Oct 2018 15:56:27 GMT

A great explanation. I managed to stumble my way through some of this on my own late last night. I shall try again following this and see how it goes.