<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Labs 4-5-6 done! Path to the end???</title><link>/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/labs-4-5-6-done-path-to-the-end</link><description>I have finished Labs 4, 5, and 6! About:Through Avnet, Xilinx and Element14, a training program to learn about the Zynq 7000 platform which is System On Chip combining an FPGA with an ARM processor. This comes to the students as complete develop...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Labs 4-5-6 done! Path to the end???</title><link>https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/labs-4-5-6-done-path-to-the-end</link><pubDate>Sun, 02 Dec 2018 16:40:55 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3aab10a0-e7c0-405d-93cf-cb5ba1752421</guid><dc:creator>rscasny</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;James,&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Thanks for a great blog. One of the reasons I picked you for this program was that while you had a good technical background, you weren&amp;#39;t as well versed on FPGAs. But your efforts to learn and the great comments your blog here has inspired is a great eye opener to understanding how to master programmable logic devices, etc. &lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Randall&lt;/p&gt;&lt;p&gt;-element14&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5864&amp;AppID=209&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Labs 4-5-6 done! Path to the end???</title><link>https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/labs-4-5-6-done-path-to-the-end</link><pubDate>Thu, 08 Nov 2018 14:14:29 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3aab10a0-e7c0-405d-93cf-cb5ba1752421</guid><dc:creator>Fred27</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;&lt;em&gt;&amp;quot;&lt;span&gt;Block Ram is essentially virtual ram within the FPGA. Since an FPGA can be made into &amp;quot;anything&amp;quot;, this is one of the options.&amp;quot;&lt;/span&gt;&lt;/em&gt;&lt;/p&gt;&lt;p&gt;&lt;span&gt;I&amp;#39;m a total beginner at this so could well be wrong, but I don&amp;#39;t think this is quite correct. I thought RAM created using the FPGA fabric (i.e. creating lots of D flip flops) is called distributed RAM. Block RAM is dedicated RAM sections inside the PL.&lt;/span&gt;&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5864&amp;AppID=209&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Labs 4-5-6 done! Path to the end???</title><link>https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/labs-4-5-6-done-path-to-the-end</link><pubDate>Thu, 08 Nov 2018 12:16:57 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3aab10a0-e7c0-405d-93cf-cb5ba1752421</guid><dc:creator>aspork42</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;It might be a good question for someone working at a PCB manufacturer - I was curious about the same thing. I know that where I used to work we had to make text fixtures for each and every PCB we made. I never worked on any that had FPGAs though. I know that I would certainly be using boundary scan if I had ordered a prototype board. This certainly seems like the easiest way validate that the traces are routed correctly.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5864&amp;AppID=209&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Labs 4-5-6 done! Path to the end???</title><link>https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/labs-4-5-6-done-path-to-the-end</link><pubDate>Thu, 08 Nov 2018 08:46:54 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3aab10a0-e7c0-405d-93cf-cb5ba1752421</guid><dc:creator>Gough Lui</dc:creator><slash:comments>1</slash:comments><description>&lt;blockquote class="jive-quote"&gt;&lt;p&gt;I am again very thankful to Element 15 and Xilinx for putting this training together!&lt;/p&gt;&lt;/blockquote&gt;&lt;p&gt;Yep ... that element of surprise &lt;span&gt;[View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-3aab10a0-e7c0-405d-93cf-cb5ba1752421/contentimage_5F00_1.png:16:16]&lt;/span&gt;.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;On another note, nice to see what all the course labs are covering content wise. I wonder how much of boundary scan is actually being used in a practical means for testing of PCBs/IC soldering/chip-to-chip connections in reality and how one might actually go about specifying the signals they &amp;quot;expect&amp;quot; to see under a given drive condition.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;- Gough&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=5864&amp;AppID=209&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>