RE: [PP-08] Lab 5 - Adding a peripheral in programmable logic

michaelkellett — Sun, 11 Nov 2018 11:06:48 GMT

This is all very well, but could you please explain the point of it all.

You've connected both ports of a block RAM to the Zynq processor - via an AXI block RAM controller - according to the introduction this will buffer data going between the PS to the PL.

For those of us not steeped in Xlinx jargon,

What are the PS and the PL and how does the block diagram, is this a complete thing, and what does it actually do ?

I can't see any way that data gets out from the BRAM to Programmable Logic (my guess at what PL is).