Working with DMA through AXI between DDR and PL BlockRAM

RE: Working with DMA through AXI between DDR and PL BlockRAM

prasad.kumawat.22 — Wed, 03 Feb 2021 09:25:09 GMT

Hi, [mention:390bd829517d47b8b6a57a2c29a935f1:e9ed411860ed4f2ba0265705b8793d05] I saw in most of the images that you are importing examples from a folder called "Speedway/ZynqHW/ZynqDesign." Will you please let me where I can get the source or can you please direct me on how will be able to get the direction to those lab exercises.

RE: Working with DMA through AXI between DDR and PL BlockRAM

14rhb — Sun, 29 Sep 2019 08:28:56 GMT

Hi [mention:390bd829517d47b8b6a57a2c29a935f1:e9ed411860ed4f2ba0265705b8793d05] I noticed your post when you published it and bookmarked it for later reading....and sorry I then forgot. I'm currently working on my Z7k Logic Analyser: Progress Update #2 and I am now finding your post very interesting and useful. Thank you for the great explanation of these building blocks, BRAM, DMA and the AXI.

RE: Working with DMA through AXI between DDR and PL BlockRAM

DAB — Sun, 18 Nov 2018 20:25:26 GMT

Did you do any timing tests for these test cases and compare them to non-DMA transfers of the same size?

DAB