/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/lab-9---final-hw-lab---tcl-me-some-moreYou may remember when we left off, we removed the JTAG interface from our board design, but we left the PWM module and the Logic Analyzer, so the Block Design looked like this: and I said something about next lab we would do some more TCL ...en-USTelligent Community 12https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/lab-9---final-hw-lab---tcl-me-some-moreTue, 04 Dec 2018 20:25:12 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:bdadeae4-b6f8-4147-ac4a-a2f23cc66b6cDAB0<p>Nice update.</p><p>&nbsp;</p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=6048&AppID=209&AppType=Weblog&ContentType=0" width="1" height="1">