RE: Xilinx ZYNQ - Blog 5 - Advanced eXtensible Interface (AXI) and Using Block RAM

DAB — Mon, 24 Dec 2018 21:49:33 GMT

Very good update.

It reminds me of doing bit-slice design work back in the 1970's.

DAB

RE: Xilinx ZYNQ - Blog 5 - Advanced eXtensible Interface (AXI) and Using Block RAM

genebren — Mon, 24 Dec 2018 00:18:41 GMT

Nice write-up. Nothing like a board full of raw, configurable power! I too used a Xilinx CPLD to create a dual ram block project. I did an implementation that had two blocks of RAM, one which could be filled during and acquisition phase and the other that could be read and processed and sent to a USB port (prior acquisition cycle). Then the blocks would swap (address flip) and the process would repeat. I all worked like a champ until Windows got to busy (keep the screen pretty or printing something) and then data would drop.

I hope that your path to programmable is going well and that you are learning plenty of new things.

Gene