<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Path to Programmable - SW Lab 0, Lab 1, Lab 2</title><link>/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/path-to-programmable---sw-lab-0-lab-1-lab-2</link><description>Welcome to the second half!This is the second half of the Zynq training series. The first half covered the &amp;quot;hardware&amp;quot; side of things; meaning the physical FPGA, the AXI Interface, and a fair amount of &amp;quot;TCL&amp;quot; (pronounced &amp;quot;tickle&amp;quot;) interface. In the sec</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Path to Programmable - SW Lab 0, Lab 1, Lab 2</title><link>https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/path-to-programmable---sw-lab-0-lab-1-lab-2</link><pubDate>Wed, 09 Jan 2019 19:56:05 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:d45805dd-5d79-4170-bc35-5464523763c8</guid><dc:creator>rscasny</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice intro to the SW module.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=6190&amp;AppID=209&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>