/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/xilinx-zynq---blog-6---creating-custom-ip-a-pwm-module-in-verilogNote: This is part 6 of a series on working with FPGAs and in particular the Xilinx Zynq-7000S Programmable System-on-Chip with ARM Cortex-A9 processing core. For part 1, click here: Xilinx ZYNQ System-on-Chip - Getting to know the MiniZed Board Foren-USTelligent Community 12https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/xilinx-zynq---blog-6---creating-custom-ip-a-pwm-module-in-verilogThu, 27 Dec 2018 20:13:25 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8fd116c6-9e8d-4159-9d25-2dee81f05915DAB1<p>Very clear description of how this capability was implemented.</p><p>&nbsp;</p><p>Well done.</p><p>&nbsp;</p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=6191&AppID=209&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/xilinx-zynq---blog-6---creating-custom-ip-a-pwm-module-in-verilogThu, 27 Dec 2018 13:38:59 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8fd116c6-9e8d-4159-9d25-2dee81f05915genebren1<p>Great update on your path to programming journey.&nbsp; It is good to see some Verilog and VHDL getting generated.&nbsp; The tools do seem to be powerful and helpful.</p><p>&nbsp;</p><p>Good luck on your future lessons.</p><p>Gene</p><img src="https://community.element14.com/aggbug?PostID=6191&AppID=209&AppType=Weblog&ContentType=0" width="1" height="1">