FPGA - 04 - Testing the BRAM and Intro to custom IPs !

FPGA - 04 - Testing the BRAM and Intro to custom IPs !/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/fpga---04---testing-the-bram-and-intro-to-custom-ipsHey folks,ZynqHW_2017_4_lab_6_v12.pdf So let's continue our arduous journey through the lab manuals. Boy, aren't things spicing up a bit?So the first part of lab 6 shows us to import our SDK files done from Lab 3. The main aim was just t...en-USTelligent Community 12RE: FPGA - 04 - Testing the BRAM and Intro to custom IPs !https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/fpga---04---testing-the-bram-and-intro-to-custom-ipsThu, 24 Jan 2019 20:32:18 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:5b9c5cc0-3b09-42cf-b00e-d2c89a516d57DAB2<p>Nice update.</p><p> </p><p>DMA should be very simple to set up and use.</p><p>Did you look into the timing issues associated with a DMA lockout cycle on the basic software execution?</p><p> </p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=6360&AppID=209&AppType=Weblog&ContentType=0" width="1" height="1">