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MiniZed: Developing Zynq Software with Xilinx software Development Kit 2019.1

dennisw1009 — Sun, 09 May 2021 20:25:44 GMT

while I'm waiting for hardware, I started software download, two questions here

1. I got a desktop for my disposal, so I installed ubuntu 16.04 (I guess that should be the same as using Windows 10 then installed ubuntu 16.04 as VM), will that serve the purpose? (or I have to buy windows 10 pro, install it then install VM for ubuntu 16.04)

2. when I download everything, I only found the link for Zynq_SW_2019_1_student_v01.zip, where/how can I find Zynq_HW_2019_1_student_v01.zip?

thanks for help

Dennis Wang

Lab 8 - Was VIO covered?

aspork42 — Sun, 25 Nov 2018 03:24:07 GMT

In the intro to Lab 8; there was mention of three different types of debugging - JTAG2AXI; VIO; and ILA. Did I miss VIO? Or is that a part of the Integrated Logic Analyzer?

Path-to-Programmable Trainees: How's It Going and Next Steps

rscasny — Wed, 14 Nov 2018 01:58:40 GMT

To all Path to Programmable Trainees.

I going through all your blogs and they are pretty interesting. I'll be making comments on them in the next couple of days. I see most of you are on track so I wanted to ask you, how's it going? Was this program what you expected? Or something else?

As far as next steps, it looks like some of you are close to ready for the next module. So, I will be sending it out to you in the next week.

Thanks for your efforts.

Randall Scasny

Path-to-Programmable Program Manager

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

michaelkellett — Mon, 19 Nov 2018 14:25:16 GMT

Keep up the good work !

I look forward to seeing more about your project.

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

mu.udhay — Mon, 19 Nov 2018 14:15:18 GMT

Thank you Michael for your Correction , I will now onward refer it as Minized itself .

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

michaelkellett — Mon, 19 Nov 2018 08:51:37 GMT

PSoC (with that capitalization) is a trade mark of Cypress for their family of micro controllers with a little tiny bit of programmable logic.

It can be very confusing if you use the same term to describe the Zynq which is a different thing altogether.

https://en.wikipedia.org/wiki/Programmable_system-on-chip

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

rscasny — Sun, 18 Nov 2018 19:16:39 GMT

sure. go ahead.

Randall

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

mu.udhay — Sun, 18 Nov 2018 19:15:05 GMT

Hi Randall,

The Speedway Training is great but i felt that tools are very powerful and giving a lot of abstraction of how we implement some designs in a PSoC and i enjoyed working with them.

I would like to ask you if i can post the content about the implementation details of the project i am working on along with the training with this PSoC so that it would give some unique taste to readers .

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

rscasny — Sun, 18 Nov 2018 18:39:19 GMT

I've been watching the progress (or lack of progress) of everyone. It looks like at least some of you are ready for the next module. So, I'll starting sending it this week.

As far as your question/comment regarding" not much on logic gates" and "a lot on tool use (Vivado)....."

I went into this project knowing that some of you would have little knowledge of FPGAs and some of you would have had decent knowledge or familiarity of FPGAs. I wanted both types of people; I wanted to see how you handled the training in both cases.

The training does assume you know something about the hardware (FPGA, Soc). But your comment makes me want to ask the question: if someone has an electrical or electronic engineering degree, how much times in your course-major classes were spent on programmable logic devices, by percentage? My next question would be, if you do not have an ee degree, do you have a CS degree? If so, do you feel the course covers enough information such that you can do something (a project) even though you may not know the intricate details of the hardware?

On a separate not, I'd like to respond to your comment on a different level. Full disclaimer: the following is my impression and/or opinion....

Since I have meetings with the sponsor, I am given presentations (which one could consider training though that's not the intent) so I can better understand their direction. This helps me help them create projects. One of the problems of adopting programmable logic design has been the need to know the hardware. This problem has bigger than I even suggest. Software engineers traditionally have been at a disadavantage because hardware has not always been their specialty. Well, this is changing. They are starting to build platforms that have frameworks which contain levels of abstraction and overlays or "wrappers" such that software engineers can do PLD hardware design without intimately knowing the hardware; but tool knowledge would be essential. This field is evolving rapidly and I anticipate that programmable logic hardware design will require less hardware knowledge than in decades past.

Randall

-Path to Programmable Program Manager

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

kk99 — Sat, 17 Nov 2018 13:21:24 GMT

Hi team,
I have done all laboratories from module one. The module one is very well written and everything is nicely explained. From each laboratory we are able to learn how the SoC works and how to use it to achieve best performance. After this module we have basic knowledge about MiniZed/Zynq and Vivado.

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

aspork42 — Sat, 17 Nov 2018 04:28:15 GMT

I'm on the way to finishing up soon as well. My plan had been to finish the modules this week; but that isn't going to happen at this point; not until next week. At any rate; as a few of us have mentioned, the training is a lot about "how to use Vivado" and not really about the nuts and bolts about how an FPGA works. I don't have any formal experience programming FPGAs so this has been a big learning curve for me (as expected; and it has been fun!). So when they start talking about Verilog, for example, I spend some time researching that and how it works.

I would say that this training assumes that the learner already knows a decent amount about the hardware and this will teach them how Vivado works. It shows things like how to add peripherals like BRAM, import hardware templates and so on, but not a lot of detail on what those items really are; and especially not how & when to use them. There has been almost nil mention of logic gates; which kind of sit at the core of what FPGAs can do.

Can we get more details about the next module? What about the project? I'm ready to order a bunch of stuff to build what I had been planning (a line follower) but wasn't sure if we would be guided towards some more specific type of thing.

And - could we get new dates posted based on the current status?

Thanks again!

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

snidhi — Thu, 15 Nov 2018 09:37:57 GMT

Hello All,

I have been down with flu for the last couple of days. I have to also finish the last few labs.

I think this weekend should be time enough to do the tests and prepare the blogs as well.

Cheers

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

rsc — Wed, 14 Nov 2018 20:03:41 GMT

Hi Randall,

I'm on the last 2 labs in the first module, although I haven't been able to work on them this week so far.

I'll try and finish up this weekend.

Scott

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

Fred27 — Wed, 14 Nov 2018 19:35:47 GMT

I'm not a trainee but I'm enjoying following along with P2P. Some of the blogs are really helpful and I appreciate all the effort that's being put into them.

I suspect the next module will also not concentrate on the PL itself but will focus on the software side of the PS.

RE: Path-to-Programmable Trainees: How's It Going and Next Steps

shabaz — Wed, 14 Nov 2018 15:28:44 GMT

Hi Randall,

I've been surprised how well the training is written and presented.

I've done a fair bit of training material preparation in the past, and it's always a fine balance between satisfying the teaching requirements, reducing the risk of errors and frustration, and recognising that engineers will always go off on their own and ignore the steps occasionally : ) it's just a natural part of being an engineer, to want to explore and learn more, so the trainer anticipates that.

In terms of the technical content, so far there is more on working with the Zynq rather than actual VHDL, but I had a feeling that would be the case since it's not feasible to learn much VHDL at the same time as the massive task of learning how the SoC works and how to use it in Vivado. I think for the Zynq/Minized, we're learning what is needed in an acceptable order so far.

I wouldn't say the course is easy, there are some concepts that have to be just accepted until the user gets further and is in a position to go back to understanding those concepts, but it is manageable with very little prior knowledge needed.

The blogs are taking a while to write, because there is a balance between learning and then reporting what we've been doing, and sharing some aspects of how to do it. It has been very helpful that we're all working on this at the same time with a common goal paced out each week.

I think it will be sufficient for a project.. I've started thinking about what I'd like to do for that, I still need to decide.

In terns of the hardware, the Minized is nice.. I'd like to integrate it into a few projects.

RE: SDK with Windows 10 problem

snidhi — Sun, 28 Oct 2018 11:43:03 GMT

I had the issue that sometimes when I launched the SDK from Vivado the SDK folder would be made and then suddenly SDK shut down automatically without a warning.

I refreshed and restarted the SDK standalone and just went ahead with the recent design file. I am also using Windows 10

Cheers

RE: SDK with Windows 10 problem

Fred27 — Tue, 23 Oct 2018 15:14:03 GMT

It's painfully slow to open, isn't it? And not even a splash screen whilst you wait to show that you have done it.

It also seems strange that it takes ages to synthesize a design compared to compiling some code - especially considering the potential speed gains when running it.

SDK with Windows 10 problem

rsc — Tue, 23 Oct 2018 13:26:31 GMT

I've been having a problem with the SDK while trying to complete the labs. When I start a new application and select one of the templates such as Hello World, the SDK closes after it makes the directories. I have to restart the SDK to download and run. Is anyone else having this problem? It doesn't happen every time though, sometimes it just minimizes the SDK window while it's compiling.

Scott

RE: SDK with Windows 10 problem

rsc — Tue, 23 Oct 2018 14:38:02 GMT

I'll look at that next time, Vivado takes 26 seconds to start up also, have you seen that? I wonder if this PC is having page faults or swap issues.

It looks like my CPU usage goes to %100 when the SDK is first launched, especially if I have a training video running in the background.

Scott

RE: SDK with Windows 10 problem

shabaz — Tue, 23 Oct 2018 14:05:03 GMT

Hi Scott,

I've not seen that yet, but I've only created one application based on the template. I'll try tonight to create several more applications, in an attempt to replicate what you're seeing.

I'm running windows 10 too.

I'm not very good at Windows 10 app troubleshooting, I'm wondering does the Windows Event Viewer maybe reveal any clue at the times it occurred?

Here are the Trainees; Thanks to All Who Applied

rscasny — Mon, 17 Sep 2018 20:26:34 GMT

We finally posted the official trainees of our Path to Programmable program. You can see them here:

Path to Programmable: Trainees Announcement

There were 132 applicants. Since there were so many great applications, we increased the official trainees from five to 8, including two alternates.

I want to thank everyone who applied.

Sincerely

Randall Scasny

-element14

The Path to Programmable Winners Have Been Selected; Announcement Coming Soon

rscasny — Fri, 14 Sep 2018 17:24:56 GMT

There were 132 applications in our Path to Programmable training program. This came down to 106 pages of MS word pages! A lot of information to go through!!

I read each application 3 times to make sure everyone was equally considered for this training program.

There were many, many great applications. Most people followed our procedure and answered the five additional questions. Thanks.

I've selected the winners with a few changes. Since there were so many good applicants, I expanded the trainees from 5 to 8. (element14 paid for the three additional MiniZed boards.)

So, eight people were selected, as well as two alternates.

The official announcement will be coming very soon.

Thanks for all who applied.

Sincerely,

Randall Scasny

-element14

RE: The Path to Programmable Winners Have Been Selected; Announcement Coming Soon

gsgill112 — Mon, 17 Sep 2018 12:03:42 GMT

I think, Winners might Have already received the eMails. But, Nothing like an Official Announcement.

//Guri

RE: The Path to Programmable Winners Have Been Selected; Announcement Coming Soon

sathasivam — Mon, 17 Sep 2018 04:55:31 GMT

I was checking everyday after the dateline, lost hope when I didn't see any updates. Came back today to see the winner's blogs but surprised and glad to see Randall's post. There's still hope. Thanks Randall for the effort and time in selecting the winners and thanks element14 for sponsoring the 3 additional winners!

RE: The Path to Programmable Winners Have Been Selected; Announcement Coming Soon

dukesos@hotmail.com — Sun, 16 Sep 2018 14:39:34 GMT

Great stuff