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Current Revision posted to Documents by migration.user on 10/1/2021 6:10:04 PM

Path to Programmable: Trainees Announcement

pchan — Fri, 25 Jan 2019 15:50:00 GMT

Current Revision posted to Documents by pchan on 1/25/2019 3:50:00 PM

Welcome to the Path to Programmable Trainees Page!

Our Path to Programmable training project, in collaboration/association with Avnet and Xilinx, has now launched. The 8 trainees will use the MiniZed TMMiniZed TM as the base for creating their project. These trainees will receive FREE training along with their MiniZed^TM.

Due to receiving so many high quality applications, element14 has decided to increase the number of trainees from 5 to 8 applicants.

Please join us in congratulating the 8 Trainees! We look forward to reading all of their initial blogs and their projects after the training.

aspork42

USA

Member since 2017

Bio: James is an engineer in Research & Development. His Community participation has included: being a Design Challenge winner, posting discussions, and blogs.

Interest in the training: "I would love to delve into the depths of FPGA/SoC development. I've had plenty of experience over the years with creating my own embedded code on Arduinos and Raspberry Pis and the like, but have never developed using this type of processor."

James O'Gorman's project blogs

kk99

Poland

Member since 2011

Bio: Kamil is an engineer in Research & Development. His Community participation has included: RoadTests, blogs, discussions, videos, and polls.

Interest in the training: "I have learned the basics of FPGA during my studies. Now I am trying to learn more about FPGA devices on my own. I would like to create simple projects to improve my knowledge."

Kamil Kubacki's project blogs

mconners

USA

Member since 2012

Bio: Michael is a software developer. His Community participation has included: Roadtests, blogs, and discussions.

Interest in the training: "I feel that I'm an excellent candidate for this training because I have exposure, yet not expertise with programmable logic, I know I can learn it, I can communicate effectively, and it is a subject that I have a great deal of interest in."

Michael Conners's project blogs

rsc

USA

Member since 2016

Bio: R. Scott is a research engineer. His Community participation has included: RoadTests, Design Challenges, blogs, videos, polls, and discussions.

Interest in the training: "I solve problems every day as a research engineer. I just finished a 3 week experiment on a research vessel in the Indian Ocean, where I was in charge of several instruments, including a Rockland VMP 500, and support for our stabilization platform. I've designed and built dozens of projects over the years from automated test stands to weather stations, networking with RPi and mbed."

R. Scott's project blogs

snidhi

Germany

Member since 2017

Bio: S. Nidhi is an engineer in Research & Development. Her Community participation has included: RoadTests, blogs, videos, and discussions.

Interest in the training: "My programmable knowledge is a bit old and rusty and I am planning to continue giving it a new life with this training session at element14. My idea for the final project in the Path to Programmable training is to design a simple version of the Super Mario Brothers game in the Avnet MiniZed Development Board with real-time image processing. It was one of the first games I owned and played as a child. I have had my eyes locked onto this gaming project using programmable logic for sometime now and have done some research on it."

S. Nidhi's project blogs

shabaz

Member since 2011

Bio: Shabaz is an engineer in the technical marketing field. His Community participation has included: Top Member, element14 Member of the Year (2014, 2016), Design Challenges, RoadTests, blogs, videos, polls, and discussions.

Interest in the training: "I have not worked with a processor core inside an FPGA before, but I think many people will be in that situation, and therefore curious to see my progress. I am very familiar with Linux, and some device driver experience, so I think this could be relevant to make the most of programmable logic with a processor core."

Shabaz Yousaf's project blogs

mu.udhay

India

Member since 2018

Bio: Udhay is a student. This is his first time participating in the Community.

Interest in the training: "I am an EE undergraduate student. I love Digital Systems Design which made me learn to write synthesizable VHDL code. My fascination towards PLDs and ASICs made me learn Practical Controllers Design in order to build a better system based on the given Constraints and tradeoffs."

Udhay Kumar Mugati's project blogs

avnrdf

India

Member since 2016

Bio: Avner is a student. His Community participation has included: Design Challenges, RoadTests, blogs, discussions, and videos.

Interest in the training: "I've taken courses on digital design in college, and am currently attending a VLSI/FPGA course this semester. I'm particularly interested in this course because not only does the course cover the usage of Zynq hardware (PS+PL, AXI etc.), but also how to use Xilinx's software: various Vivado/SDK features like Tcl scripting & Xilinx IP which are very important for someone graduating college, since development software features is usually neglected in college."

Avner Fernandes's project blogs

nixiefairy

Ireland

Member since 2017

Bio: Eashan is a student. His Community participation has included: RoadTests, comments, videos, and discussions.

Interest in the training: "It has been a love / hate relationship with FPGAs, with the hate slowly converting to love. My first FPGA kit experience was a year ago, on a Spartan 3E Kit. I feel that with a structured course, not only will I have a proper learning but also I will be able to blog and record structured notes. The best part of blogs is that there are instant reviews from a larger audience and one can correct course immediately."

Eashan Wadhwa's project blogs

dotmish

USA

Member since 2014

Bio: David is an Embedded Medical Device Developer. This is his first time participating in the Community.

Interest in the training: "I have about 25 years of experience developing safety critical real-time embedded medical devices, and more recently (as a hobby) learning about Software Defined Radio, which is of interest because I hold a General Ham Radio License. My goal with this course would be to greatly improve my understanding of FPGAs, with the intention of developing an open source Software Defined Radio Transceiver that operates in the 2 meter, 1.25 meter, and 70 centimeter ham bands."

David Mishler's project blogs

Interested in following along with the Trainees? Here's how:

Follow their posts to learn more about the FPGA/SoC. You can purchase the MiniZed TMMiniZed TM to recreate the projects of the trainees or feel free to comment.

Good Luck Everyone!

Tags: path to programmable: trainees announcement, soc, fpga, avnet_featured

Path to Programmable: About Training Project

pchan — Mon, 03 Dec 2018 17:13:22 GMT

Current Revision posted to Documents by pchan on 12/3/2018 5:13:22 PM

Path to Programmable

If this is NOT a Design Challenge, what is the 'Path to Programmable' training project? Here's the story...

Origins of the Project

About a year ago, the element14 team turned its attention to Programmable Logic Devices (PLDs). Given the depth of content and breadth of projects on the Community, we saw PLDs as an area of electronics that deserved a lot more attention. Thus, we began sponsoring discussions on designing with programmable devices, and with the help of Avnet we sponsored RoadTests and hosted a related webinar. But it was really our members' comments about the reality of designing with PLDs that motivated us to launch this professional development training project.

What Our Members Told Us about PLDs

Through our member discussions, we learned about PLDs from a developer's point of view. One of our Top Members stressed the need to find the right end-application that truly required a PLD as a key factor in choosing a PLD over a processor in hardware design. Another member stressed the importance of a change in mindset from sequential programming to logical building blocks. Finally, nearly all of our members agreed that there is a significant learning curve needed to master the tools necessary to program PLDs. It was this last discussion point—the learning curve challenge—that the element14 team found interesting, and we thought it merited a deeper exploration. The outcome of this exploration was the birth of the Path to Programmable training project.

What Is the Goal of the Project?

The Path to Programmable training project will train five element14 members by providing them with free FPGA/SoC training modules with lab exercises. Once the training has been completed, the trainees will build a project with the MiniZed^TM development board based on what they have learned.

In return for both the FREE training and the MiniZed^TM development board, the five trainees will blog regularly on element14 to report about their learning experience, covering both the high points and the challenges of learning to program FPGA/SoC devices. The blogs will be read by the community and the project's sponsor to learn more about how to make the path to developing with programmable devices easier to realize.

What Will the Trainees Learn?

Any element14 member can apply to be a Path to Programmable sponsored trainee, but there are prerequisites, so please read the Application Instructions page before submitting an application. A course syllabus has been posted on the Course Syllabus page.

The Board

The official trainees will receive an Avnet MiniZed^TM Development Board to complete the lab exercises and build their graduation project.

The official trainees are limited to 5 applicants. But you can purchase the board below if you simply are interested in following along with the trainee blogs and the course syllabus.

Buy NowBuy NowTech Specs

How To Apply?

Any element14 member can apply to be a Path to Programmable sponsored trainee. But there are prerequisites and specific questions to be answered in the application, so please read the Application Instructions page before submitting an application.

Important Dates

The training project will cover three phases: (I) enrollment, (II) training with labs, and (III) project building. The important dates are:

Enrollment Begin:	July 26 2018
Enrollment Ends:	August 27 2018
RoadTesters Selected:	September 1 2018
Training Begins:	September 7 2018
Training Ends:	October 21 2018
Project Building Begins:	October 28 2018
Project Building Ends:	January 14 2019

Blogging Requirement

One of the key ways we can understand the learning curve challenge of designing with PLDs is for our trainees to provide us feedback about their training experience. Hence, they will be REQUIRED to blog frequently, from the start of the training through the completion of the project building phase. We want to learn about the high points and challenges of their experience, and this is critical to understanding the learning curve challenge that so many people experience when first trying to build hardware with PLDs.

Technical Assistance

As with any skills-building experience, there will be times when you need to rely on someone for help. To assist our trainees, we have arranged for mentors from our sponsor Xilinx, Avnet, and from senior element14 Community members. Please visit the Mentors page to learn more.

Graduation Awards

As a thank you for participating in the training project, and completing the training and project building, we will offer the trainees these graduation awards:

Designing with Xilinx® FPGAs: Using Vivado

FLUKE 3000 FC - Wireless Digital Multimeter

Pro's Kit Electronic Tool Kit

Special Note

The Path to Programmable is NOT a Design Challenge. It is a professional development training project sponsored by Xilinx in conjunction with the element14 Community. element14 members who submit applications are competing to receive FPGA/SoC training only.

For any general questions about the Path to Programmable training project, please post a comment on this page.

To keep up-to-date with the Path to Programmable training project, please bookmark this project.

The deadline for application submissions is 27 August 2018.

Tags: soc, path to programmable, xilinx, path_to_programmable, training_project, avnet_featured, about_this_challenge

Path to Programmable: Terms and Conditions

pchan — Mon, 03 Dec 2018 17:13:01 GMT

Current Revision posted to Documents by pchan on 12/3/2018 5:13:01 PM

Path to Programmable

This is NOT a Design Challenge. See Special Note below.

The Path to Programmable project will train five element14 members and provide them with free FPGA/SoC training modules with lab exercises. Once the training has been completed, the trainees will build a project with the MiniZed^TM development board based on what they have learned.

In return for both the FREE training and the MiniZed^TM development board, the five trainees will blog regularly on element14 to journal about their learning experience, covering both the high points and the challenges of learning to program FPGA/SoC devices. The blogs will be read by the community and the sponsors to learn more about how to make the path to developing with programmable devices easier to realize.

Terms and Conditions

Like most other projects on element14 that require an application, the Path to Programmable project has established rules that the applicants must follow.

Rules ensure fair play and prevent abuse, among other purposes. These rules are described in detail in the project's Terms and Conditions. You can read the Path to Programmable training project's terms by downloading the attached PDF.

Special Note

The Path to Programmable is NOT a Design Challenge. It is a professional development project sponsored by Xilinx in conjunction with the element14 community. element14 members who submit applications are competing to receive FPGA/SoC training only.

For any general questions about the Path to Programmable project, you can post a comment on the About page.

To keep up-to-date with the Path to Programmable project, please bookmark this project.

The deadline for application submissions is 27 August 2018.

Attachments:

community.element14.com/.../Path-to-Programmable-Terms-and-Conditions.pdf

Path to Programmable Terms and Conditions.pdf

Tags: path to programmable: terms and conditions, soc, fpga, path_to_programmable, terms_and_conditions

Path to Programmable: Mentors

pchan — Mon, 17 Sep 2018 20:08:39 GMT

Current Revision posted to Documents by pchan on 9/17/2018 8:08:39 PM

Path to Programmable

This is NOT a Design Challenge. See Special Note below.

The Path to Programmable training project will train five element14 members and provide them with free FPGA/SoC training modules with lab exercises. Once the training has been completed, the trainees will build a project with the MiniZed^TM development board based on what they have learned.

What are Mentors?

They will assist the five sponsored trainees in mastering the course material and/or lab exercises, and will provide guidance during the project building phase of the training program. The following individuals have offered their time and services for any assistance that may be needed.

Sponsor's Mentors

Both Xilinx and Avnet will make available experts to assist our trainees, if necessary. A specialist judge from Xilinx and Avnet will be giving their expert feedback and advice on FPGA/SoC.

element14 Community Mentors

alvieboy

Álvaro Lopes has been a member of element14 since 2013. He is an engineer who works in the aerospace industry. He provides end customers solutions which integrate CPUs and programmable logic - the Xilinx Zynq family is one of the platforms he uses. He is the author of a full System-on-a-Chip (SoC) for FPGAs - ZPUin, which is in production and supports FPGAs from several vendors.

weiwei2

Cheah Wei Leow has been a member of element14 since 2012. He currently works on MATLAB application engineering for clients in South East Asia. He was a calibration software R&D engineer with Agilent Technologies (now Keysight) with over 15 years of experience in test and measurement instruments and data acquisition systems. He has special expertise in the field of embedded systems, computer vision and machine learning.

grosar

George Rosar has been a member of element14 since 2016. He is a retired engineer with special expertise in the field of telemetry. From a lifetime of engineering, he has a wide variety of interests, including audio, broadcast, communications, consumer electronics, computing, energy harvesting, industry, medical, power management, and security.

MARK2011

Marek Cherubin has been a member of element14 since 2011. He is a Chief Energy Specialist engineer in the biggest Polish district heating company: Veolia Energia Warszawa. He works in the R&D department Heat Tech Center, and collaborates with the faculty of the Power and Aeronautical Engineering of Warsaw University of Technology.

Thank you to the Mentors for offering their time and service, as well as being on hand to respond to questions. The element14 Community Team with help oversee the judges and challengers during the training process.

Special Note

For any general questions about the Path to Programmable project, you can post a comment on the About page.

To keep up-to-date with the Path to Programmable project, please bookmark this project.

The deadline for application submissions is 27 August 2018.

Tags: soc, path to programmable: mentors, path_to_programmable

Path to Programmable: Application Instructions

pchan — Mon, 17 Sep 2018 20:07:47 GMT

Current Revision posted to Documents by pchan on 9/17/2018 8:07:47 PM

Path to Programmable

This is NOT a Design Challenge. See Special Note below.

Eligibility

You must be an element14 member to be eligible. Go here to register. All element14 members are welcome to apply.

Application Form

All interested members must submit an application via the Design Challenge group before the end of enrollment. (Note: We are using the Design Challenge group because the application infrastructure is in place and easy for our members to use, but this is NOT a Design Challenge.)

Application Instructions

1. Please complete all required information (contact information, etc.)

In the Project Title field, just fill in "Path to Programmable Applicant or your Member Name"

Please use the email address that is associated with your element14 profile. In the event that you use another address, please provide your member name in the Project Title field.

2. Complete the open comments section of the form.

Like a Design Challenge application, you will need to tell us why you want to be selected as a sponsored trainee for the Path to Programmable training project. When you plan what you are writing, think about the following things:

You are competing for a place. The most persuasive applications are the ones that attract the eye of the selection team.
A single sentence application will never be selected as an official trainee. This project, like training projects, is not a game of chance.
Be as detailed as possible, but don't write a book.

3. In addition to the information requested in points 1 and 2 above, please include in your comments answers to the following questions:

What is your background in FPGAs, SOCs, or programmable devices?
What development tools have you used with programmable devices?
Describe your embedded design experience. (You can talk about courses you have taken, work experience, examples of projects, etc.)
What kind of problem solver are you? (Expert, Very Experienced, Experienced, Student). Describe a problem you have solved.
Describe how you participate in the element14 Community. Examples of programs, projects, blogs, etc. can be included.
Do you have the time and availability to commit to this approximately 12-week project that will require you to: watch the training videos, complete the lab exercises, and build a project. (If you have to work in the field for extended periods, have family commitments, or are expected to have a health issue (i.e., surgery) during the project, you may want consider if you can indeed complete the program.)

Special Note

For any general questions about the Path to Programmable project, you can post a comment on the About page.

To keep up-to-date with the Path to Programmable project, please bookmark this project.

The deadline for application submissions is 27 August 2018.

Tags: application_instructions, soc, instruction, path_to_programmable

Path to Programmable: Course Syllabus

pchan — Mon, 17 Sep 2018 20:06:54 GMT

Current Revision posted to Documents by pchan on 9/17/2018 8:06:54 PM

Path to Programmable

This is NOT a Design Challenge. See Special Note below.

Description of Training

The five sponsored trainees will receive 2 training modules, with accompanying training videos, lab exercises, and a MiniZed^TM to complete the labs.

Here is the course syllabus:

Module 1: Developing Zynq All Programmable (AP) SoC Hardware

Objectives

Understand the Zynq-7000 All Programmable SoC development flow with Vivado’s IP Integrator
Introduce the single ARM Cortex™-A9 Processors Cores
Explore Robust AXI Peripheral Set
Utilize the Xilinx embedded systems tools to
Design a Zynq AP SoCSystem
Add Xilinx IP as well as custom IP
Run Software Applications to test IP
Debug an Embedded System

Lessons

Zynq Overview
Xilinx Embedded Tool Flow
Zynq Processor Overview
Peripherals, Peripherals and more Peripherals!
The Power of Tcl
Merging the Processing Subsystem (PS) and Programmable Logic (PL)
Zynq PS DMA Controller
Creating Custom IP
Vivado’s Hardware Manager
Tcl Scripting
What’s Next

Module 1 Labs

Pre-Lab: Setting Up a Development Platform for Zynq
Introduction to Zynq Hardware: Building a Basic Zynq Design
Introduction to Zynq Hardware: PS Configuration Part 1 - HelloWorld
Introduction to Zynq Hardware: PS Configuration Part 2 MIO Peripherals
Introduction to Zynq Hardware: Using Tcl in Vivado Embedded Designs
Introduction to Zynq Hardware: Adding a PL Peripheral June 2017
Introduction to Zynq Hardware: Improving Data flow between PL and PS utilizing PS DMA
Introduction to Zynq Hardware: Adding Custom IP to Vivado IP Catalog
Introduction to Zynq Hardware: Hardware Debugging Zynq Designs Xilinx Embedded Tool Flow
Introduction to Zynq Hardware: The Power of Scripting using Tcl

Module 2: Developing Zynq All Programmable (AP) SoC Software

Objectives

Introduce developers to Xilinx SDK
Explore how SDK makes your job easier
Connect SDK to hardware for execution and debug
Show a basic example of using the single processor
Utilize a peripheral interrupt to show real-time software response

Lessons

Zynq System Architecture Basics
Xilinx SDK Overview
Standalone Board Support Package
Developing Applications
Connecting Hardware and Debugging
First Stage Boot Loader
Flash Programming and Boot up
SDK project management
Interrupts
Xilinx Libraries
Integrating TE Connectivity’s HTU21DHTU21D Sensor Pmod

Module 2 Labs

Developing Zynq Software with Xilinx SDK: Pre-Lab Setting Up a Development Platform for Zynq
Developing Zynq Software with Xilinx SDK: Explore a Zynq Hardware Platform
Developing Zynq Software with Xilinx SDK: Importing the Hardware Platform into SDK
Developing Zynq Software with Xilinx SDK: Bare Metal Board Support Package
Developing Zynq Software with Xilinx SDK: Develop a Zynq Software Application
Developing Zynq Software with Xilinx SDK: Connecting SDK to Hardware
Developing Zynq Software with Xilinx SDK: First Stage Boot Loader (FSBL)
Developing Zynq Software with Xilinx SDK: Boot from Flash
Developing Zynq Software with Xilinx SDK: SDK Project Management
Developing Zynq Software with Xilinx SDK: Interrupts
Developing Zynq Software with Xilinx SDK: Xilinx Libraries
Developing Zynq Software with Xilinx SDK TE HTU21DHTU21D Pmod Standalone Environment

Special Note

For any general questions about the Path to Programmable project, you can post a comment on the About page.

To keep up-to-date with the Path to Programmable project, please bookmark this project.

The deadline for application submissions is 27 August 2018.

Tags: soc, path_to_programmable, course_syllabus