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<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/atom.xsl" media="screen"?><feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en-US"><title type="html">Blog</title><subtitle type="html" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/atom</id><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog" /><link rel="self" type="application/atom+xml" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/atom" /><generator uri="http://telligent.com" version="12.1.9.35025">Telligent Community (Build: 12.1.9.35025)</generator><updated>2022-01-24T16:51:00Z</updated><entry><title>LiFi #5 - Block Explanation</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-5---block-explanation" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-5---block-explanation</id><published>2022-02-01T04:35:00Z</published><updated>2022-02-01T04:35:00Z</updated><content type="html">LiFi #5 Block Explanation


Table of Contents

&lt;a href="#mcetoc_1frfv63f2p"&gt;Abstract&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f2q"&gt;Modules&lt;/a&gt;

&lt;a href="#mcetoc_1frfv63f2r"&gt;LIR interface&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f2s"&gt;BOUND Detector&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f2t"&gt;ID Buffer&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f2u"&gt;Length Extractor&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f2v"&gt;Data Field&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f210"&gt;CRC XMODEM&lt;/a&gt;


&lt;a href="#mcetoc_1frfv63f211"&gt;Registers&lt;/a&gt;

&lt;a href="#mcetoc_1frfv63f212"&gt;CONFIG&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f213"&gt;STATUS&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f214"&gt;RECEIVED ID&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f215"&gt;DATA SPLITTER&lt;/a&gt;


&lt;a href="#mcetoc_1frfv63f216"&gt;Peripheral Assembly&lt;/a&gt;
&lt;a href="#mcetoc_1frfv63f217"&gt;Simulation Testbenches&lt;/a&gt;

&lt;a href="#mcetoc_1frfv63f218"&gt;ID test&lt;/a&gt;
...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-5---block-explanation"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22964&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>kluivertcorreia</name><uri>https://community.element14.com/members/kluivertcorreia</uri></author><category term="xilinx" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/xilinx" /><category term="Digilent Cmod S7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Digilent%2bCmod%2bS7" /><category term="lifi" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/lifi" /><category term="verilog" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/verilog" /></entry><entry><title>LiFi #4 - Custom LiFi Peripheral</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-4---custom-lifi-peripheral" /><link rel="enclosure" type="application/pdf" length="48539" href="https://community.element14.com/cfs-file/__key/telligent-evolution-components-attachments/01-346-00-00-00-02-29-63/LiFi_2D00_frontend.pdf" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-4---custom-lifi-peripheral</id><published>2022-02-01T04:11:00Z</published><updated>2022-02-01T04:11:00Z</updated><content type="html">LiFi #4: Custom LiFi Peripheral


Table of Contents

&lt;a href="#mcetoc_1fraen46u9"&gt;Abstract&lt;/a&gt;
&lt;a href="#mcetoc_1fraen46ua"&gt;Protocol&lt;/a&gt;

&lt;a href="#mcetoc_1fraen46ub"&gt;Inspiration&lt;/a&gt;
&lt;a href="#mcetoc_1fraen46uc"&gt;Framing&lt;/a&gt;
&lt;a href="#mcetoc_1fraen46ud"&gt;Boundaries&lt;/a&gt;


&lt;a href="#mcetoc_1fraen46ue"&gt;Frontend Circuit&lt;/a&gt;

&lt;a href="#mcetoc_1fraen46uf"&gt;Limitations&lt;/a&gt;


&lt;a href="#mcetoc_1fraen46ug"&gt;Design Flow Overview&lt;/a&gt;
&lt;a href="#mcetoc_1fraen46uh"&gt;Conclusion&lt;/a&gt;



Abstract
As promised in an earlier edit, this is the UPDATE I wanted to make t...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/lifi-4---custom-lifi-peripheral"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22963&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>kluivertcorreia</name><uri>https://community.element14.com/members/kluivertcorreia</uri></author><category term="xilinx" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/xilinx" /><category term="lifi" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/lifi" /><category term="digilent" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/digilent" /><category term="verilog" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/verilog" /></entry><entry><title>Blog 1: Anomaly detection using CMOD 7 FPGA</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/blog-1-anomaly-detection-using-cmod-7-fpga" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/blog-1-anomaly-detection-using-cmod-7-fpga</id><published>2022-01-31T18:46:00Z</published><updated>2022-01-31T18:46:00Z</updated><content type="html">Initial thoughts and things planned:
After the industrial revolution in the 18th-century machines are vital parts of humans and they are very much essential to fulfill the demands of the fast-growing world. We as engineers should try to
reduce the co...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/blog-1-anomaly-detection-using-cmod-7-fpga"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22957&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>vishwasn</name><uri>https://community.element14.com/members/vishwasn</uri></author><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="Digilent Cmod S7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Digilent%2bCmod%2bS7" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /></entry><entry><title>Getting started with digilent FPGA Board With Xilinx Vivado.</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/getting-started-with-digilent-fpga-board-with-xilinx-vivado" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/getting-started-with-digilent-fpga-board-with-xilinx-vivado</id><published>2022-01-31T15:32:00Z</published><updated>2022-01-31T15:32:00Z</updated><content type="html">Getting started with digilent FPGA Board With Xilinx Vivado. Here I am explaining steps to create a simple project Using FPGA And Xilinx Vivado Software. In this project, I am Using Cmod S7 Onboard LED And Buttons To show an example.
Here I am Explai...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/getting-started-with-digilent-fpga-board-with-xilinx-vivado"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22953&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>vinayyn</name><uri>https://community.element14.com/members/vinayyn</uri></author><category term="xilinx" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/xilinx" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="Digilent Cmod S7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Digilent%2bCmod%2bS7" /><category term="basic" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/basic" /><category term="verilog" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/verilog" /></entry><entry><title>Audio Synth #7 - Design challenge ends, project continues</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-7---design-challenge-ends-project-continue" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-7---design-challenge-ends-project-continue</id><published>2022-01-31T03:15:00Z</published><updated>2022-01-31T03:15:00Z</updated><content type="html">Table of Contents

&lt;a title="Audio Synth #1 - The project" href="/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-1---the-project-202798230"&gt;Audio Synth #1 - The project&lt;/a&gt;
&lt;a title="Audio Synth #2 - Board introduction and IDE setup" href="/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-2---board-intro-and-ide-setup" rel="noopener noreferrer" target="_blank"&gt;Audio Synth #2 - Board introduction and IDE setup&lt;/a&gt;
&lt;a title="Audio Synth #3 - Arduino to CmodS7 COMM Test" href="/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-3---fpga-to-arduino-comm" rel="noopener noreferrer" target="_blank"&gt;Audio Synth #3 - Arduino to CmodS7 COMM Test&lt;/a&gt;
&lt;a title="Audio Synth #4 - Use PWM to control LED" href="/challenges-projects/design-challenges/b/blog/posts/audio-synth-4-use-pwm-to-control-led" rel="noopener noreferrer" target="_blank"&gt;Audio Synth #4 - Use PWM to control LED&lt;/a&gt;
&lt;a title="Audio Synth #5 - Testing the I2S PCM5102 DAC Decoder Board" href="/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-5---testing-the-i2s-pcm5102-dac-decoder-board" rel="noopener noreferrer" target="_blank"&gt;Audio Synth #5 - Testing the I2S PCM5102 DAC Decoder Board&lt;/a&gt;
&lt;a title="Audio Synth #6 - Sound generation with CmodS7" href="/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-6---sound-generation-with-cmods7" rel="noopener noreferrer" target="_blank"&gt;Audio Sy...&lt;/a&gt;(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-7---design-challenge-ends-project-continue"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22949&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>a33333</name><uri>https://community.element14.com/members/a33333</uri></author></entry><entry><title>Security Camera #1: Project Proposal</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-1-project-proposal-629530496" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-1-project-proposal-629530496</id><published>2022-01-30T14:15:00Z</published><updated>2022-01-30T14:15:00Z</updated><content type="html">Blog 1: Project Proposal
This 6-part blog series will go over the project build-up for a simple security camera. FPGA camera projects best&amp;nbsp;demonstrate the parallel capability of FPGAs when interfacing with a high throughput device like a camera....(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-1-project-proposal-629530496"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22956&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Security Camera #6: Project Demonstration and Final Words</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-6-project-demonstration-and-final-words" /><link rel="enclosure" type="application/octet-stream" length="43295385" href="https://community.element14.com/cfs-file/__key/telligent-evolution-components-attachments/01-346-00-00-00-02-29-40/Security_5F00_Camera.zip" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-6-project-demonstration-and-final-words</id><published>2022-01-30T05:20:00Z</published><updated>2022-01-30T05:20:00Z</updated><content type="html">Blog 6: Project Demonstration and Final Words
Yes, we are now down to my final blog. The goal of this last blog is to show how to use my project, demonstrate the project in action, and have some final words. Materials needed?

&lt;a href="https://digilent.com/reference/programmable-logic/cmod-s7/start"&gt;CMOD S7 FPGA&lt;/a&gt;
&lt;a href="https://digilent.com/reference/vivado/getting_started/2018.2"&gt;XIlinx Viv...&lt;/a&gt;(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-6-project-demonstration-and-final-words"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22940&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Security Camera #5: Adding Peripheral Sensors</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-5-adding-peripheral-sensors" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-5-adding-peripheral-sensors</id><published>2022-01-30T03:44:00Z</published><updated>2022-01-30T03:44:00Z</updated><content type="html">Blog 5: Adding Peripheral Sensors
We successfully connected the OV7670 camera to the SD card driver for storage of images. Now its time to make our camera smarter by adding sensors! The goal of this fifth blog is to interface sensors in our Security ...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-5-adding-peripheral-sensors"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22939&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Security Camera #4: Interfacing with OV7670 Camera</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-interfacing-with-ov7670-camera" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-interfacing-with-ov7670-camera</id><published>2022-01-29T06:19:00Z</published><updated>2022-01-29T06:19:00Z</updated><content type="html">Blog 4: Interfacing with OV7670 Camera
Now that we have the driver for the SD card where the images will be stored to, it is now time for the main event. The goal of this fourth blog is to to be able to interface with the OV7670 camera.
OV7670 is the...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-interfacing-with-ov7670-camera"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22935&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Security Hardware Accelerator #7 SHA256 in UART port</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-hardware-accelerator-7-sha256-in-uart-port" /><link rel="enclosure" type="application/zip" length="2944" href="https://community.element14.com/cfs-file/__key/telligent-evolution-components-attachments/01-346-00-00-00-02-29-30/sha256_5F00_hash_5F00_hw.zip" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-hardware-accelerator-7-sha256-in-uart-port</id><published>2022-01-29T01:34:00Z</published><updated>2022-01-29T01:34:00Z</updated><content type="html">1. Brief
In previous blog, SHA256 has been elastrated and acomplished in software core and hardware core.&amp;nbsp;
Only with independant port, can sha256 accelerator runs. There have been choice of SPI, I2C, USB or UART. Fully understand of protocle is ...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-hardware-accelerator-7-sha256-in-uart-port"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22930&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>fyaocn</name><uri>https://community.element14.com/members/fyaocn</uri></author></entry><entry><title>Security Camera #3: Testing the SD Card Driver</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-testing-the-sd-card-driver-367553867" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-testing-the-sd-card-driver-367553867</id><published>2022-01-29T00:47:00Z</published><updated>2022-01-29T00:47:00Z</updated><content type="html">Blog 3: Testing the SD Card Driver
If you have read my first two blogs, I&amp;#39;m sure you are feeling bored by now. But don&amp;#39;t you worry, today will be more hands-on. The goal of this third blog is to verify that the SD card driver is working. Mate...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-3-testing-the-sd-card-driver-367553867"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22931&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Analog signal processing on FPGA #2 - Integration of the MicroBlaze IP core into the FPGA</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/analog-signal-processing-on-fpga-2---integration-of-the-microblaze-ip-core-into-the-fpga" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/analog-signal-processing-on-fpga-2---integration-of-the-microblaze-ip-core-into-the-fpga</id><published>2022-01-28T14:32:00Z</published><updated>2022-01-28T14:32:00Z</updated><content type="html">In this part, I will describe how I integrated the MicroBlaze IP core into the FPGA.
I have Vivado 2019.1 installed. There is a good description of how to install Vivado and Board File here:&amp;nbsp;&lt;a href="https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-sdk"&gt;https://digilent.com/reference/programmable-logic/ gui...&lt;/a&gt;(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/analog-signal-processing-on-fpga-2---integration-of-the-microblaze-ip-core-into-the-fpga"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22923&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>maxpowerr</name><uri>https://community.element14.com/members/maxpowerr</uri></author><category term="spartan 7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/spartan%2b7" /><category term="xilinx" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/xilinx" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="vivado" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/vivado" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="microblaze" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/microblaze" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>Security Camera #2: SD Card Interfacing</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-2-sd-card-interfacing-52194343" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-2-sd-card-interfacing-52194343</id><published>2022-01-28T08:20:00Z</published><updated>2022-01-28T08:20:00Z</updated><content type="html">Blog 2: SD Card Interfacing

Before we dive into camera interfacing, we must first ready the SD card where we will save the images. The aim of this second blog is to have a working SD Card driver in pure Verilog HDL.

How to Interface with an SD Card...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/security-camera-2-sd-card-interfacing-52194343"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22921&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>angelo76</name><uri>https://community.element14.com/members/angelo76</uri></author><category term="Security Camera" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Security%2bCamera" /><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /><category term="cmod s7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/cmod%2bs7" /></entry><entry><title>HACK CPUMOD S7 #5: Peripheral Remapping</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-5-peripheral-remapping" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-5-peripheral-remapping</id><published>2022-01-27T20:51:00Z</published><updated>2022-01-27T20:51:00Z</updated><content type="html">This time the HACK uC has a new memory map,

as the table shows, this memory map includes two BSP components; SWITCH and LEDS. The SWITCH register only maps one of the buttons in the board, BTN1, the other one corresponds to computer reset. The LEDS ...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-5-peripheral-remapping"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22913&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>pandoramc</name><uri>https://community.element14.com/members/pandoramc</uri></author><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="Digilent Cmod S7" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/Digilent%2bCmod%2bS7" /><category term="HACK CPU" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/HACK%2bCPU" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /></entry><entry><title>HACK CPUMOD S7 #4: PWM Module extension</title><link rel="alternate" type="text/html" href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-4-pwm-module-extension" /><id>https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-4-pwm-module-extension</id><published>2022-01-24T22:51:00Z</published><updated>2022-01-24T22:51:00Z</updated><content type="html">Consider the IP Catalog, mainly the Clocking Wizard. For this component we can stablish an input clock of 12MHz, as the boards has, and the output is multipled by power of two values.

This allow a power up in the clock speed, consequently, the PWM c...(&lt;a href="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/hack-cpumod-s7-4-pwm-module-extension"&gt;read more&lt;/a&gt;)&lt;img src="https://community.element14.com/aggbug?PostID=22864&amp;AppID=346&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</content><author><name>pandoramc</name><uri>https://community.element14.com/members/pandoramc</uri></author><category term="fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/fpga" /><category term="HACK CPU" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/HACK%2bCPU" /><category term="summer of fpga" scheme="https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/archive/tags/summer%2bof%2bfpga" /></entry></feed>