/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/number-plate-recognition-3-implementing-block-ram-using-verilogFor making our project we need to work with images and for storing images inside an FPGA we need to use Block RAM. So, in this section, I will show how to implement Block RAM in FPGA using the Vivado tool. What is Block RAM? Block RAMs (or BRAM) stanen-USTelligent Community 12https://community.element14.com/challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/number-plate-recognition-3-implementing-block-ram-using-verilogSat, 11 May 2024 13:05:42 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:61cc3972-954a-40a8-8d03-3764d079ae20bincy0<p>hello</p> <p>can you please share detailed cide in verilog</p><img src="https://community.element14.com/aggbug?PostID=22753&AppID=346&AppType=Weblog&ContentType=0" width="1" height="1">