https://community.element14.com/challenges-projects/project14/musictime/Build Projects Involving Clocks and Musical Instruments!en-USTelligent Community 12https://community.element14.com/challenges-projects/project14/musictime/b/blog/posts/prize-package-receivedTue, 13 Jun 2023 17:56:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f3fb673a-7ede-407a-bdb1-ac8adab32195aspork42I used my $200 shopping cart from this contest to pick up a new Multicomp Pro portable oscilloscope MP720015 is the model. I've wanted to have a non-mains referenced scope for a while and this works perfectly. Now I can probe a little safer This model is a dual unit - Digital multi-meter and oscilloscope. It was handy to switch between. In the image below, I'm trouble shooting a power supply from a PoE Switch. Perhaps that can be the subject of a future blog. Thanks to the E14 crew for all of this!prizeoscilloscopemusic timeprize packagehttps://community.element14.com/challenges-projects/project14/musictime/m/managed-videos/147461Fri, 14 Apr 2023 21:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:973c6d81-6468-43e9-a56d-7b272db8c7e5redcharlyhttps://community.element14.com/challenges-projects/project14/musictime/b/blog/posts/musical-boxFri, 14 Apr 2023 21:46:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:c21b7e69-4473-446d-b7eb-bce8f8b7f74aredcharlyMusical Box Introduction This project was created to participate in a contest and we have modified it and enriched it with features. Even now we are working to add new features in the little free time we can find. I love music and it accompanies me in all the important moments of my life. This project uses a Cypress Semiconductor CY8CKIT-041-41XX PSoC® 4100S Pioneer Kit and a Raspberry Pi 4 to build a simple Music Machine. The operating principle is simple: let's imagine, for example, distributing the musical genres we prefer on an x,y plane, then positioning the songs according to the genre. Just click on the trackpad and the song will start with the coordinates closest to those of the clicked position. Once the song is finished, the song closest to the clicked position among those remaining is played. Obviously, the user can decide whether to change the genre (by clicking on a new area of the trackpad) or move to the next song. It will also be possible to vary the volume using the trackpad. For example, we could associate the x-axis with speed ( low x corresponds to "slow" music, love songs, while high x values represent "fast" songs, for example Rock songs. The Y axis could instead represent a quality index, for example, low values of y could represent pop music, while higher values represent Jazz. The work of classifying the songs is very important and, based on how it is done, we will obtain different results. An interesting classification for long stays in the car could be, for example, this, staring at the bottom left for love songs, for example, Elton John, at the bottom right for rock songs (Queen, Eagles, etc.), at the top right for fast rock songs (Deep Purple, Metallica), top left Jazz pieces (Miles Davis, John Coltrane, etc.). The project The project was created using only two devices. We used the CY8CKIT-041-41XX PSoC® 4100S Pioneer Kit to build the user interface. The device is really interesting and we have only used the trackpad for now. Its modular construction allows you to use it even in an external case, it is in fact made as two distinct sections, that of the sensors and the control unit which are connected via a flat cable. It is very simple to use the components of this device in a complex project.. The task performed by this module is only to collect the commands provided by the user, for example, the position on the "music map", or the simple operations that we can perform, such as adjusting the volume or changing the track. The code was created starting from the examples provided by Cypress which allows you to use the trackpad with the "click" , "swipe" and "rotation" functions. Edge Swipe Right, Click, Edge Swipe Left, Rotate Clockwise, Rotate Counterclockwise, Touchpad Area The second device used was a Raspberry Pi 4 which is used to make the mp3 file player. We'll use simple Python code to handle the playback of the audio tracks. In particular, the pygame library that manages mp3 files with extreme simplicity and reliability has been of great help. The connection between the two devices was made with a simple serial connection. Song classification All the songs to be used must be contained in a folder whose position must be declared in the Python code. Each song will have a prefix consisting of two numbers between 0 and 99 that represent the Cartesian (x and y) coordinates of the song in the trackpad plane. The trackpad has a sensitive area represented by a matrix of 100x100 points and the association between the song and its "position", i.e. its x and y coordinates, must be made by the user according to one's preferences, through a "musical map ". I have thought of a few but the choice depends on everyone's musical tastes and, based on their musical preferences, everyone will be able to create their own "musical map", where to place the songs. A rather boring job is to classify the music, i.e. associate a pair of coordinates to each song based on the criteria adopted. It could be very interesting to automatically classify the songs using an Artificial Intelligence system, such as Edge Impulse which, from the spectral components of the song, can extract the x and y coordinates for correct placement of the song in the x, and y plane of our musical map. The code We had to program the CY8CKIT-041-41XX PSoC® 4100S Pioneer Kit and the Raspberry Pi 4. To program the trackpad we used PSoC Creator while we used Python to create the Musical Box on the Raspberry. https://youtu.be/8_5rlr2tAK4 Conclusion It was so much fun making this project. I hope I haven't bored you too much and thanks to Genesis for the blog title.raspberrymusictimechmusicpsochttps://community.element14.com/challenges-projects/project14/musictime/b/blog/posts/building-fpga-based-music-instrument-synthesis-a-simple-test-bench-solutionFri, 14 Apr 2023 21:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:4ade5d55-4598-4b10-a2e9-e3a1183db480javagozaIntroduction For the past two months, I have been publishing a series of blogs introducing concepts such as Direct Digital Frequency Synthesis (DDFS), 1-bit Delta Sigma Digital to Analog Converters (DAC), and Attack, Decay, Sustain, Release (ADSR) envelope generators, with the upcoming topic of random noise generation. This project serves as a way to consolidate my initial learnings and create a small test bench for experimentation with time-based sound synthesis and noise generation. DDFS. Direct Digital Frequency Synthesis for Sound FPGA ADSR envelope generator for sound synthesis (I) AMD Xilinx 7 series FPGAs XADC https://youtu.be/aqtAe7n2ooc Music Time: Justifying the FPGA-based Music Instrument Synthesis System Design This system designed as a test bed for the synthesis of musical instruments based on FPGA is closely linked to the concept of "musical time". Timing plays a critical role in the precise generation and synchronization of waveforms, to ensure that musical notes are played at the right time and in precise pitch. By using the Direct Digital Synthesis (DDFS) technique, digital waveform data points are generated and converted to analog signals, which are then filtered and shaped to produce an audio output. Additionally, the system uses techniques such as an ADSR envelope generator to shape sound waves over time, allowing for dynamic and expressive musical sounds, allowing something close to the sound of real instruments to be mimicked. The synchronization of waveforms and effects within the FPGA enables the creation of complex audio effects or multi-timbral musical instruments, further reinforcing the close relationship between the system design and the concept of "music time". The system The FPGA-based music instrument synthesis system presented here can produce different types of sound waves, like sine, square, sawtooth, triangle, and noise. These waves can be changed and shaped using a technique called ADSR, which adjusts how the sound starts, fades, sustains, and stops. It uses a method called Direct Digital Synthesis (DDFS) to create these waves digitally. Then, it converts them to analog signals using a 1-bit Delta Sigma Digital to Analog Converter (DAC) and a Low Pass Filter (LPF). This allows us to have precise control over the generated sounds and mimic musical instruments and effects. The system is based on the Digilent Arty S7 50 development board, which features an AMD Spartan-7 FPGA. It incorporates a simple RC low-pass filter and utilizes six potentiometers for parameter control. The readings from the potentiometers are captured using the XADC component from the series 7 FPGA, allowing control over the audio synthesis parameters. The audio output is connected to an amplified speaker, allowing for the synthesized sounds to be heard in real-time with amplified volume. User interface The user interface of the system consists of four buttons for selecting different notes, four slide switches for changing the octave, and six analog potentiometers for adjusting various parameters, including the ADSR parameters such as attack time, decay time, sustain level, sustain time, and release time, as well as the waveform type (such as sine, square, sawtooth, triangle, and random noise). This interface allows for control over the synthesized sounds, enabling users to shape the sound and create different musical effects. 6 analog potentiometers to control sound parameters HDL Design The project is heavily inspired by the book "FPGA Prototyping by SystemVerilog Examples" by Pong Chu, which has been instrumental in my introduction to FPGA hardware design using the SystemVerilog hardware description language (HDL). All the module development in SystemVerilog, as well as the test bench for the modules and synthesis, have been carried out using the AMD Xilinx Vivado development tool. Main Module The main module: Instantiates one ILA module for debugging Instantiates one xadc ip module for reading the analog inputs from the Potentiometers voltage dividers Instantiates one ADSR module Instantiates one DDFS module Instantiates one Moving Average LPF module Instantiates one Delta Sigma 1-bit DAC module Converts 5 ADC readings to ADSR parameters for the ADSR module Converts 1 ADC reading to waveform type for the DDFS module Responds to slide switches events: changing the octave of the note frequency of the DDFS Respond to push button events: changing the control frequency of the DDFS SystemVerilog implementation `timescale 1ns / 1ps module checkXadcAdsrNoise( input clk, input logic [3:0] sw, input logic [3:0] btn, input logic vp_in, // input wire vp_in input logic vn_in, // input wire vn_in input logic vauxp0, // input wire vauxp0 input logic vauxn0, // input wire vauxn0 input logic vauxp1, // input wire vauxp1 input logic vauxn1, // input wire vauxn1 input logic vauxp2, // input wire vauxp2 input logic vauxn2, // input wire vauxn2 input logic vauxp3, // input wire vauxp3 input logic vauxn3, // input wire vauxn3 input logic vauxp8, // input wire vauxp8 input logic vauxn8, // input wire vauxn8 input logic vauxp9, // input wire vauxp9 input logic vauxn9, // input wire vauxn9 input logic vauxp10, // input wire vauxp10 input logic vauxn10, // input wire vauxn10 input logic vauxp11, // input wire vauxp11 input logic vauxn11, // input wire vauxn11 output audio_out, // audio out output gain, // Gain output pulse_out, output neg_shutdown, // ~SHUTDOWN output logic [5:0] led ); localparam T = 2; localparam W = 16; localparam PHASE_ACC_WIDTH = 30; localparam M1 = 30'h0AFD; // (262.0 / 100_000_000.0) * (1 modu is Q18.14 // * convert modu back to Q16.0 always_comb begin case (wave_type[2:0]) 3'b000: amp = sin_amp; 3'b010: amp = square_amp; 3'b001: amp = saw_amp; 3'b011: amp = triangle_amp; 3'b100: amp = noise_amp; endcase modulation = $signed(envelope) * $signed(amp); end assign pcm_out = pcm_reg; assign pulse_out = phase_reg[PHASE_ACC_WIDTH-1]; assign pulse_noise = phase_reg[PHASE_ACC_WIDTH-5]; endmodule ADSR module The ADSR scheme is based on the observation that when a real instrument generates a note, the volume of the musical note changes over time. It rises rapidly from zero and then steadily decays. The ADSR scheme is based on the observation that when a real instrument generates a note, the volume of the musical note changes over time. It rises rapidly from zero and then steadily decays. To model this effect we can multiply the constant tone produced by the DDFS module by an amplitude ADSR envelope that contains the segments, attack, decay, sustain and release See: (+) SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I) - Blog - FPGA - element14 Community for more info about this module The ADRS envelope can be specified by two amplitude parameters, A max and Asus, and four time parameters, Attack time, Decay time, Sustain time and Release time. A max: maximum amplitude level the envelope can reach. A sus: the amplitude of the sustain segment. Attack time: the time interval of the Attack segment. Decay time: the time interval of the Decay segment. Sustain time: the time interval of the Sustain segment. Release time: the time interval of the Release segment. SystemVerilog implementation. `timescale 1ns / 1ps // fsm to generate ADSR envelop // start (trigger) signal: // - starts the "attack" when asserted // - restarts the epoch if aseerted before the current epoch ends // amplitudes: // - 32-bit unsigned // - use 32 bits to accommodate the needed resolution for "step" // - intepreted as Q1.31 format: // - range artificially limited between 0.0 and 1.0 // - i.e., 0.0...0 to 1.0...0 (1.0) // - 1.1xx...x not allowed // output: Q2.14 for range (-1.0 to 1.0) // special atk_step values // - atk_step = 11..11: bypass adsr; i.e., envelop=1.0 // - atk_step = 00..00: output 0; i.e., envelop = 0.0 // Width selection: // max attack time = 2^31 * clock period = 2^31 *(1/100e6) = 21,47483648 seconds // Attack_time // t_attack desired attack time // t_sys sytem clock period // maximum amplitude Amax // need t_attack / t_sys clock cycles in the attact segment // the counter must be incremented (Amax - 0)/(t_attack - t_sys) each clock cycle to reach A_max from zero in t_attack // Decrementing amount in decay segment for t_decay // t_decay and A_sus. (A_max-A_sus) / (t_sustain / t_sys) // // Decrementing amount in release segment // (A_sus - 0)/(t_release - t_sys) // The amplitude is constant in the sustain segment // There are are tsustain / t_sys cycles in the sustain segment // Amax | /\ // | / \ // | / \ // Asus | / ------------ // |/ \ // --------------------------- // | attack // | decay // | sustain // | release module adsr( input logic clk, input logic reset, input logic start, // generate a pulse to start the envelope generation input logic [31:0] attack_step_value, // precalculated (Amax - 0)/(t_attack - t_sys) steps for the attack segment input logic [31:0] decay_step_value, // precalculated (A_max-A_sus) / (t_sustain / t_sys) steps for the decay segment input logic [31:0] sustain_level, // amplitude for the sustain segment input logic [31:0] release_step_value, // precalculated (A_sus - 0)/(t_release - t_sys) steps fot the release segment input logic [31:0] sustain_time, // tsustain / t_sys steps for the sustain output logic [15:0] envelope, output logic adsr_idle ); // constants localparam MAX = 32'h8000_0000; localparam BYPASS = 32'hffff_ffff; localparam ZERO = 32'h0000_0000; // fsm state type typedef enum {idle, launch, attack, decay, sustain, rel} state_type; // declaration state_type state_reg; state_type state_next; logic [31:0] amplitude_counter_reg; logic [31:0] amplitude_counter_next; logic [31:0] sustain_time_reg; logic [31:0] sustain_time_next; logic [31:0] n_tmp; logic fsm_idle; logic [31:0] envelope_i; // state and data registers always_ff @(posedge clk, posedge reset) begin if(reset) begin state_reg sustain_level) begin amplitude_counter_next = n_tmp; end else begin amplitude_counter_next = sustain_level; state_next = sustain; sustain_time_next = 32'b0; // start timer end end end sustain: begin if (start) begin state_next = launch; end else begin if(sustain_time_reg release_step_value) begin amplitude_counter_next = amplitude_counter_reg - release_step_value; end else begin state_next = idle; end end end endcase end assign adsr_idle = fsm_idle; assign envelope_i = (attack_step_value == BYPASS) ? MAX : (attack_step_value == ZERO) ? 32'b0 : amplitude_counter_reg; assign envelope = {1'b0, envelope_i[31:17]}; endmodule Noise Generator Module Noise is characterized as being aperiodic or having a non-repetitive pattern. White noise is a type of sound that contains all audible frequencies in equal amounts. It sounds like a hiss or a static noise. In sound synthesizers, white noise is used as a starting point for creating other sounds. By adding filters or modulating the sound, the synthesizer can create different tones or textures. A few examples of sounds that can be created using white noise as a starting point are: t he sound of a snare drum, the sound of the wind. the sound of ocean waves, the sound of cymbals... For noise generation this module uses a linear-feedback shift register (LFSR). An LFSR is a shift register whose input bit is a linear function of its previous state. The most commonly used linear function of single bits is exclusive-or (XOR). Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value. Any long LFSR counter generates a long pseudo-random sequence of zeros and ones. The sequence is not exactly random since it repeats eventually, and it also follows a mathematically predictable sequence. Vivado synthesis for the SystemVerilog module The appropriate taps for Maximum-Length LFSR Counters are extracted from this Xilinx Technical Note: xapp052.pdf • Viewer • AMD Adaptive Computing Documentation Portal (xilinx.com) SystemVerilog implementation of the Noise module by means of an Linear Feedback Shift Register. `timescale 1ns / 1ps // Description: // This module generates an 16-bit random number. A LFSR or Linear Feedback Shift Register // is a quick and easy way to generate pseudo-random data inside of an FPGA. module lfsr #(parameter NUM_BITS = 31) ( input logic clk, input logic reset, input logic enable, output logic [NUM_BITS-1:0] lfsr_data ); logic [NUM_BITS:1] lfsr_reg = 0; logic polinomial; // run LFSR when enabled. always @(posedge clk, posedge reset) begin if (enable == 1'b1) begin if (reset == 1'b1) begin lfsr_reg 8'h7F) begin data = {8'h00, 8'hFE - addr_r}; // decaying end else begin data = {8'h00, addr_r}; // raising end end assign dout = $signed(data > 17) + (ma_old_reg - (ma_old_reg >> 17)) ; assign lpf_out = {1'b0, ma_new_reg[31:17]}; endmodule Echo Delay Still in development this is the first version to implement an echo or feedback delay module. `timescale 1ns / 1ps module echo #(DELAY_LINE_SIZE = 1024)( input logic clk, input logic reset, input logic [15:0] in, input logic [7:0] delay, input logic [7:0] feedback, output logic [15:0] out ); logic [15:0] delay_line [DELAY_LINE_SIZE]; int write_ptr = 0, read_ptr = 0; logic [15:0] echo_signal; always_ff @(posedge clk, posedge reset) begin if(reset) begin write_ptr = 0; read_ptr = 0; end else begin // Write input to delay line and compute echo signal delay_line[write_ptr] = in; echo_signal = delay_line[read_ptr] * feedback; read_ptr = (read_ptr + delay) % DELAY_LINE_SIZE; write_ptr = (write_ptr + 1) % DELAY_LINE_SIZE; // Mix input and echo signals out = in + echo_signal; end end endmodule HDL Sources community.element14.com/.../s7_5F00_ddfs.srcs.zip Vivado Project Structure The project contains all the modules indicated in the blog as well as test bench modules for simulations. Constraints File This constraints file is adapted to the current system configuration, 4 monocolor LEDs, 2 RGB LEDs, 4 slide switches, 4 push buttons, 6 analog potentiometers used with the XADC module of the Spartan 7 FPGA and the PDM digital output to the RC low-pass analog filter. . ## This file is a general .xdc for the Arty S7-50 Rev. B ## Clock Signals set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] ## Switches set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {sw[2]}] set_property -dict {PACKAGE_PIN M5 IOSTANDARD SSTL135} [get_ports {sw[3]}] ## LEDs set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}] set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}] set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}] set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}] ## RGB LEDs #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_15 Sch=led0_g #set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_A28_15 Sch=led1_g #set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b ## Buttons set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {btn[0]}] set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {btn[1]}] set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {btn[2]}] set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports {btn[3]}] ## Pmod Header JD set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports audio_out] set_property DRIVE 16 [get_ports audio_out] set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports gain] set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports pulse_out] set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports neg_shutdown] #set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29] #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28] #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27] #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26] ## ChipKit Single Ended Analog Inputs ## NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). ## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { vauxp0 }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vauxn0 }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { vauxp1 }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1] set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { vauxn1 }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1] set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { vauxp9 }]; #IO_L5P_T0_AD9P_15 Sch=ck_an_p[2] set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { vauxn9 }]; #IO_L5N_T0_AD9N_15 Sch=ck_an_n[2] set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vauxp2 }]; #IO_L7P_T1_AD2P_15 Sch=ck_an_p[3] set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { vauxn2 }]; #IO_L7N_T1_AD2N_15 Sch=ck_an_n[3] set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { vauxp10 }]; #IO_L8P_T1_AD10P_15 Sch=ck_an_p[4] set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vauxn10 }]; #IO_L8N_T1_AD10N_15 Sch=ck_an_n[4] set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { vauxp11 }]; #IO_L10P_T1_AD11P_15 Sch=ck_an_p[5] set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vauxn11 }]; #IO_L10N_T1_AD11N_15 Sch=ck_an_n[5] ## Dedicated Analog Inputs set_property -dict { PACKAGE_PIN J10 } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p set_property -dict { PACKAGE_PIN K9 } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n ## ChipKit Digital I/O On Inner Analog Header ## NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11) set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { vauxp8 }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8] set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vauxn8 }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8] set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { vauxp3 }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3] set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { vauxn3 }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3] ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] Vivado Integrated Logic Analyzer During the development of the project I have found very useful the incorporation to the system, while debugging, of Vivado's Integrated Logic Analyzer. Here is a sample of how easy it is to integrate. In this example we spy on signals from AMD's XADC IP module. Instantiating the ILA for debugging the XADC IP // ila instantiation ila_0 ila ( .clk, .probe0(adc_data), .probe1(channel_out), .probe2(enable), .probe3(ready), .probe4(eos_out) ); Programming device attaching debug probes file Conclusions This project is a new objective fulfilled for the final goal of learning SystemVerilog HDL by creating my own synthesizer designed with FPGA. Thanks to dougw and genebren for posting their blogs on the subject that I am learning and being inspired by. Project blogs Building FPGA-Based Music Instrument Synthesis: A Simple Test Bench Solution DDFS. Direct Digital Frequency Synthesis for Sound ADSR envelope generator for sound synthesis. AMD Xilinx 7 series FPGAs XADCADSRmusictimechsquare wavefpga_projectsDDFSDirect Digital Frequency Synthesisxilinxsawtooth wavefpgawavetriangle wavedigilentmusic timesoundarty s7amdnoisesystemverilogEcho Processorsynthesizerhttps://community.element14.com/challenges-projects/project14/musictime/m/managed-videos/147460Fri, 14 Apr 2023 21:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:c3369da5-bb46-4c16-98c1-bb6e2fae68dbjavagozaBuilding FPGA-Based Music Instrument Synthesis: A Simple Test Bench Solution element14 Project14 Music Time /challenges-projects/project14/musictime/b/blog/archive/2023/04/13/building-fpga-based-music-instrument-synt...https://community.element14.com/challenges-projects/project14/musictime/m/managed-videos/147458Fri, 14 Apr 2023 05:06:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7e3f1a12-c407-4922-b288-d28f8d38d414aspork42I set up a player piano in such a way that I can use a Python script to play it. I’m using a Festo pneumatic manifold controlled via Modbus TCP and push values via Python.https://community.element14.com/challenges-projects/project14/musictime/m/managed-videos/147457Fri, 14 Apr 2023 05:06:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:c6130cf6-1814-4b2a-91cf-af9e2984be33aspork42