Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cmelement14

cmelement14 — Mon, 12 Oct 2020 01:38:35 GMT

After installed Vitis 2020.1 on Ubuntu 18.04, I tried Lab 2 and it worked. The only difference from the lab instruction is the serial terminal inside Vitis IDE doesn't work for me. And actually it crashed Vitis when the application is trying to send text to the terminal window. I think that's because I am using Linux version of Vitis. Anyways, I used an external serial terminal software called GtkTerm and I was able to see the messages.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by sambit1991

sambit1991 — Mon, 12 Oct 2020 08:34:56 GMT

Haven't received it yet.

Hope it arrives this week.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by embeddedguy

embeddedguy — Mon, 12 Oct 2020 08:37:27 GMT

For me arrived today and the tax was around 45 Euros. !!

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by navadeepganeshu

navadeepganeshu — Mon, 12 Oct 2020 08:40:56 GMT

Yes, got large custom duties imposed.

I got a notification today demanding for total charges of ~ $85 (6226 INR) as custom duties.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by sambit1991

sambit1991 — Mon, 12 Oct 2020 08:52:07 GMT

This is not fair.

Dear organizers, could you please comment on this?

Why the duty on evaluation products? Shouldn't these be free of all charges (or at least nominal charges)?

What do we need to know?

Best Regards

Sambit

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Mon, 12 Oct 2020 18:43:57 GMT

I got the boards and they don't come with USB cables, so I bought those separately.

I then bought a 2 TB Hard drive (only $5 more than the 1TB HD).

I used the quick link to down load the Xilinx files. The link says use 2020.1.

So I'm downloaded 2020.1. It says it's only works on Windows 10 Professional 64 bit. I have Windows 10 Home 64 bit. I'm gambling here now.

But THEN Oh no I read the pdf, it says load update 1 of 2020.1, which is 2020.1.1.

But, then it looks like you loaded 2020.1, which is what I'm loading, which by the way takes hours.

Will I have to upgrade to Win 10 Professional?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by egershon

egershon — Tue, 13 Oct 2020 15:22:49 GMT

When I tried to generate bit stream I get a message:

" There are no implementation results available. OK to lunch synthesis and implementation? 'Generate bitstream will automatically start when synthesis and implementation completes."

"yes", "No" options are there to select. I selected the Yes....

That was not on any of the slides

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by wmcmahon0103

wmcmahon0103 — Tue, 13 Oct 2020 19:39:45 GMT

What part of this lab 2 document is the "pre-lab" that needs to be completed before tomorrow's workshop?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Wed, 14 Oct 2020 18:01:47 GMT

Lab 2

On step 18, The the board interface for CLK_IN1 is set to sys_clk. I did this.

On step 23 I dragged System Clock which was already colored (I'm color blind, I don't know what color it is) to the Clock Wizard and got:

[IP_Flow 19-3460] Validation failed on parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1'

[IP_Flow 19-3460] Validation failed on parameter 'CLK IN2 BOARD INTERFACE(CLK_IN2_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1'

[BD 41-245] set_property error - Validation failed on parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1' Validation failed on parameter 'CLK IN2 BOARD INTERFACE(CLK_IN2_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1' Customization errors found on 'clk_wiz_1'. Restoring to previous valid configuration.

This creates a very large error.

I had to go back to clock wizard and remove sys_clk and change it back to custom.

Then add the System clock and that worked, other wise sys_clk is left floating, even though it shows in the clock wizard.

Step 34 took me ten minutes to find the generate bit stream the top bar menu button.

Pushing the button resulted in an error message" No implementation results are available","

There are no implementation results available. OK to launch synthesis and implementation?

'Generate Bitstream' will automatically start when synthesis and implementation completes.

I click OK.

I get Launch runs on local host, but the number of jobs is 2, and 6 is not available.

Run time 00.01.21.

Step 35 never showed up or closed before I looked 4 minutes later.

20 minutes later as I'm trying load the XSA that's missing, step 35 window pops up in Vivado that I'm not looking at. I press Cancel. XSA is still missing. Error messages:

Unable to get BIT file from implementation run.............................Aborting wr_hw_platform

When I try to rerun bit stream I get error message " Bitstream generation has already completed and is up-to-date. Re-run anyway?" NO.

I exported the XSA file before the compile was done. I needed to wait for the Generation Bit Stream complete!

I re-exported the XSA and everything is good again.

Step 58. Program failed. Reason: Could not find FPGA board for connection 'local'

Trouble shooting tips:

1) Check whether the board is connected to the system correctly.(I don't know, lights are flashing so board works) Do I have to change a jumper setting on the Digilent board? It comes with no instructions.

2) In case of a Zynq Board................

3) If you are suing a Xilinx platform cable USB...................

The USB comport shows up as com6, so the USB connection enumerated correctly.

At this point I am completely stumped.

OK, some Chinese guy had exactly the same problem, but I had to use Chinese to English translation.

It basically says I need to load the driver. Where do I find the driver?

There were a few installation issues I didn't read and just continued.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by wmtilton

wmtilton — Wed, 14 Oct 2020 18:40:28 GMT

I was able to use the peripheral test template to cycle through the LEDs. But I am not a C programmer, is there a template or some code for continuously reading the switches in one of the templates?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Wed, 14 Oct 2020 19:49:03 GMT

Did anybody have to change or add jumpers to make the ARTY S7 programable?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by phoenixcomm

phoenixcomm — Thu, 15 Oct 2020 00:00:57 GMT

I asked the question "can you use the eclipse IDE" Answer if you look at the VITIS IDE slide #60 (yes!) VITIS was built on top of the eclipse IDE

~~ Cris

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by jjay-xlnx

jjay-xlnx — Thu, 15 Oct 2020 08:00:26 GMT

Thank you for this workshop!

I've hit an issue after adding the dip switches to the block design, when I synthesis/generate bitstream it throws this error:

[DRC BIVRU-1] Bank IO standard Vref utilization: Bank 34 contains ports that use a reference voltage. In order to use such standards in a bank that is not configured to use INTERNAL_VREF, the bank's VREF pin must be used to supply the appropriate voltage. Example port: dip_switches_4bits_tri_i[3] (SSTL135). However, the following VREF sites are occupied and can't be used to supply the necessary voltage:

site IOB_X1Y37 (occupied by port dip_switches_4bits_tri_i[3]).

Free up VREF sites or create an appropriate INTERNAL_VREF constraint.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by sambit1991

sambit1991 — Thu, 15 Oct 2020 17:48:48 GMT

tariq.ahmad

I got a letter from DHL today asking for tons of documents for the board to be delivered.

Things are now way more difficult than I wanted them to be.

This is the translated message:

Good day,

we have an import shipment for you. For the handling of your shipment, we either need a proof of value in a suitable form about the specific content of the shipment

• Order process or order or order confirmation

• sales contract or

• Transaction receipt or PayPal statement

• or the like

Easily legible and a table of contents (with individual goods values if the shipment contains several goods items).

Please provide us with the information via our DHL4You web portal and use the following link or the QR code:

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by dhuber

dhuber — Thu, 15 Oct 2020 19:54:10 GMT

I went a little further and added the 4 slider switches to the design, but when I go to generate the bitstream I get the following error under IO Planning:

site IOB_X1Y37 (occupied by port dip_switches_4bits_tri_i[3]).

Free up VREF sites or create an appropriate INTERNAL_VREF constraint.

Any idea how to fix this?

Thanks,

Dave

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Thu, 15 Oct 2020 21:04:19 GMT

Lab 2

On step 18, The the board interface for CLK_IN1 is set to sys_clk. I did this.

On step 23 I dragged System Clock which was already colored (I'm color blind, I don't know what color it is) to the Clock Wizard and got:

[IP_Flow 19-3460] Validation failed on parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1'

[IP_Flow 19-3460] Validation failed on parameter 'CLK IN2 BOARD INTERFACE(CLK_IN2_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1'

[BD 41-245] set_property error - Validation failed on parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1' Validation failed on parameter 'CLK IN2 BOARD INTERFACE(CLK_IN2_BOARD_INTERFACE)' for Clock interface can't be same for primary and secondary input clocks . BD Cell 'clk_wiz_1' Customization errors found on 'clk_wiz_1'. Restoring to previous valid configuration.

This creates a very large error.

I had to go back to clock wizard and remove sys_clk and change it back to custom.

Then add the System clock and that worked, other wise sys_clk is left floating, even though it shows in the clock wizard.

Step 34 took me ten minutes to find the generate bit stream the top bar menu button.

Pushing the button resulted in an error message" No implementation results are available","

There are no implementation results available. OK to launch synthesis and implementation?

'Generate Bitstream' will automatically start when synthesis and implementation completes.

I click OK.

I get Launch runs on local host, but the number of jobs is 2, and 6 is not available.

Run time 00.01.21.

Step 35 never showed up or closed before I looked 4 minutes later.

20 minutes later as I'm trying load the XSA that's missing, step 35 window pops up in Vivado that I'm not looking at. I press Cancel. XSA is still missing. Error messages:

Unable to get BIT file from implementation run.............................Aborting wr_hw_platform

When I try to rerun bit stream I get error message " Bitstream generation has already completed and is up-to-date. Re-run anyway?" NO.

I exported the XSA file before the compile was done. I needed to wait for the Generation Bit Stream complete!

I re-exported the XSA and everything is good again.

Step 58. Program failed. Reason: Could not find FPGA board for connection 'local'

Trouble shooting tips:

2) In case of a Zynq Board................

3) If you are suing a Xilinx platform cable USB...................

The USB comport shows up as com6, so the USB connection enumerated correctly.

At this point I am completely stumped.

OK, some Chinese guy had exactly the same problem, but I had to use Chinese to English translation.

It basically says I need to load the driver. Where do I find the driver?

There were a few installation issues I didn't read and just continued.

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Thu, 15 Oct 2020 21:14:31 GMT

JP1, J2, are shorted, and JP13 is set to USB.

JP3, JP4 are open and are current monitor pins.

JP2 says:"When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J7 on the shield connector (these connections are not shown in Figure 6.1). It is recommended that this jumper is not shorted unless attempting to run Arduino IDE on Microblaze, because it can interfere with normal Microblaze function.

I removed JP2 and and I still get the error:

Could not find FPGA board for connection 'local'

With a Xiniz programmer you can query the J-tag port.

Can I do that from Vitis?

Jason or Tariq,

Is my ARTY bad?

How do I trouble shoot this?

Do I need a new board?

How do I get one? Do I have to buy a new or return this bad one?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Fri, 16 Oct 2020 16:13:06 GMT

I launched ISE 14.7 and used ISE iMPACT to query the board.

It finds a Xilinx part in the J-tag signal chain but the part comes up as unknow in bypass mode.

When I try to define the part, it asks for a BSDL file, of which I have no idea of what's its talking about.

So I try to define a device but it asks for Part number and specify instruction length? How do I know the instruction length?

I try to make a BSDL file, but it crashes iMPACT and closes.

I assume that know body can help me.

After 30 years of coding with assembly language and 10 years of Verilog, I guess I should just give up on new technology?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Fri, 16 Oct 2020 17:27:01 GMT

Great, What video?

re: Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes by cwrigley

cwrigley — Fri, 16 Oct 2020 17:47:47 GMT

That's what I'm doing and it doesn't work!

Both Vivado and Vitis don't recognize the ARTY board!