https://community.element14.com/learn/events/c/e/1454<p style="margin:0;"><span style="color:#333333;font-family:Arial, 'Lucida Grande', sans-serif;"><em><span><a href="https://community.element14.com/resized-image/__size/354x177/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142390.png"><img alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142390.png-354x177.png?sv=2016-05-31&sr=b&sig=urPlEDYqS9J5bw1FMQrbTTejrcHkrA3LZkPl5RcIeGI%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=Afidiyh67Edbvv8xoki8hw==" style="max-height: 177px;max-width: 354px;" /></a></span></em></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span style="color:#333333;font-family:Arial, 'Lucida Grande', sans-serif;"><em>The Vivado Design suite supports 7-Series, Zynq, and UltraScale programmable families. It is developed to address the productivity bottlenecks in system-level design, integration, and implementation. The Vivado Design suite provides ease-of-use, system level integration capabilities, and new tools and methodologies, increasing overall productivity.</em></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>To participate <a class="jive-link-external-small" href="https://www.xilinx.com/support/download.html" rel="nofollow ugc noopener" target="_blank">download Vivado 2020.1</a> and the attached lab book below!   You can also download the lab book <a class="jive-link-external-small" href="https://github.com/ATaylorCEngFIET/Getting-to-Know-Vivado" rel="nofollow ugc noopener" target="_blank">here</a>!</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">The Vivado Design Suite from Xilinx offers tools and methodologies to speed up FPGA development, while improving productivity. Within Vivado, developers can leverage C-based design, capture, simulate and implement programmable logic designs targeting Xilinx FPGA and SoCs (System-on-Chips). This three-session introduction to Xilinx Vivado Design Suite will examine how we capture designs in Vivado using both RTL entry and IP Integrator. Following design capture we will examine Vivado’s simulation capabilities that help ensure the performance of the captured design aligns with requirements. When we reach the desired functional performance level, we will move on to design implementation and programming file creation for deployment. Just as with real life, our journey does not end there. We will also explore how we can debug the implemented design on the device as it is integrated into the wider system, should the need occur.</p><p style="margin:0;padding:0px;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span><a href="https://community.element14.com/resized-image/__size/522x171/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142391.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142391.jpg-522x171.jpg?sv=2016-05-31&sr=b&sig=6Dvnp%2F%2FaQNjPECsq%2F5CPUugAtRx8i809CMlCIHyLYZ0%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=e4tsc3bizanVxeT1EWGYfg==" style="max-height: 171px;max-width: 522px;" /></a></span></p><p style="margin:0;padding:0px;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"> </p><p style="margin:0;padding:0px;"> </p><h2 style="font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:inherit;font-style:inherit;font-family:inherit;color:#3334ca;">Session 1:</span></h2><p style="margin:0;padding:0px;"> </p><p style="margin:0;">This session will consist of an overview and introduction to Vivado.  You will learn key element of FPGA design, learn about the different views inside Vivado, and explore what they can be used for.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">Topics covered include: •</p><ul><li>FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream •</li><li>What do we use Vivado for? What is its role in FPGA and SoC Development?</li><li>Design entry in Vivado -> RTL View</li><li>Simulation -> XSIM (Vivado RTL Simulation)</li><li>Implementation Flow -> Synthesis View, Implementation, Bit Stream</li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span><a href="https://community.element14.com/resized-image/__size/620x241/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142392.png"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142392.png-620x241.png?sv=2016-05-31&sr=b&sig=9cZdH2DHYoOCtsdb4Gvz0RX%2F7aRV2xjGFV2tBMMX7aw%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=RM92I6uAymYqwfJOEmi8UA==" style="max-height: 241px;max-width: 620px;" /></a></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span style="color:#333333;font-family:Arial, 'Lucida Grande', sans-serif;font-size:16px;font-weight:bold;">Dates and Register for Free:</span></p><p style="margin:0;padding:0px;"> </p><table border="1" class="jiveBorder mce-item-table" style="border:1px solid #c6c6c6;width:100%;"><thead><tr><th style="border:1px solid black;border:1px solid #c6c6c6;padding:6px;color:#505050;background-color:#f2f2f2;text-align:left;" valign="middle"><strong>Workshop:</strong></th><th style="border:1px solid black;border:1px solid #c6c6c6;padding:6px;color:#505050;background-color:#f2f2f2;text-align:left;" valign="middle"><span style="color:#505050;"><strong>Dates and Time:</strong></span></th></tr></thead><tbody><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><a name="workshops"></a><p style="margin:0;"><strong>Session 1 - Getting to Know Vivado Pt 1</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream</li><li>What do we use Vivado for? What is its role in FPGA and SoC Development?</li><li>Design entry in Vivado -> RTL View</li><li>Simulation -> XSIM (Vivado RTL Simulation)</li><li>Implementation Flow -> Synthesis View, Implementation, Bit Stream</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 26th of August 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><span style="font-weight:bold;font-family:Arial, 'Lucida Grande', sans-serif;color:#e23d39;">Register Above for Free!</span></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/313x176/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142393.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142393.jpg-313x176.jpg?sv=2016-05-31&sr=b&sig=I5hMc36MQX%2Fr6TuFW4OWLl0U60Z5ErKuoFZ8gw8990Y%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=Nq0FuVZ2awedy2iFsWrIOQ==" style="max-height: 176px;max-width: 313px;" /></a></span></strong></p></td></tr><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Session 2 - Getting to Know Vivado - Part II</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will look more closely at more commonly used features which enable designs to be generated faster.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>IP Integrator – Reduce the RTL you need to write and accelerate your design</li><li>Constraints – What is there role in the design, how do we use them?</li><li>Timing Analysis – What is timing closure, why is it important, and how do we achieve it?</li><li>Programming Configuration Memories</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 2nd of Sept 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><strong><a class="jive-link-event" href="https://www.element14.com/community/events/5612/l/xilinx-workshop-getting-to-know-vivado-part-ii">Xilinx Workshop: Getting to Know Vivado Part II</a></strong></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/312x175/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142394.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142394.jpg-312x175.jpg?sv=2016-05-31&sr=b&sig=QqDCjkMkHCnAJwggOcIbRlbBQRh6NL8%2BxYCuXdrmWV8%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=CbdgtGNli00ccHsb34D5pA==" style="max-height: 175px;max-width: 312px;" /></a></span></strong></p></td></tr><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Session 3 - Getting to Know Vivado - Part III</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will introduce advanced concepts, such as creating our own custom IPs, debugging on hardware, working with configuration control, and scripting in Vivado.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>Creating custom IP using AXI interfaces</li><li>Debugging in Vivado – ILA, VIO insertion</li><li>Working with softcore processors – MicroBlaze example</li><li>Configuration control and scripting</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 9th of Sept 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><strong><a class="jive-link-event" href="https://www.element14.com/community/events/5613/l/xilinx-workshop-getting-to-know-vivado-part-iii">Xilinx Workshop: Getting to Know Vivado Part III</a></strong></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/314x176/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142395.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142395.jpg-314x176.jpg?sv=2016-05-31&sr=b&sig=TtR9i3aBYBrwXmQ%2FrqKgmwVsi1SeT%2BgVcWQJjARADV0%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=APd3Q0Z8IQOEQrs2l80t8Q==" style="max-height: 176px;max-width: 314px;" /></a></span></strong></p></td></tr></tbody></table><p style="margin:0;padding:0px;"> </p><p style="margin:0;padding:0px;"> </p><h2><span style="color:#3334ca;">Presenter:</span></h2><p style="margin:0;padding:0px;"> </p><table border="1" class="jiveBorder mce-item-table" height="326" style="border:1px solid #ffffff;width:100%;height:265px;"><tbody><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;"><span><a href="https://community.element14.com/resized-image/__size/138x138/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142396.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142396.jpg-138x138.jpg?sv=2016-05-31&sr=b&sig=RtS%2FLkCv2ugIoLFD35bAToXPCFSHNfW3elT1ug8KmJ4%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=vrBDDDmPKqcq/LfhEaAOpg==" style="max-height: 138px;max-width: 138px;" /></a></span></td></tr><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;"><strong>Founder and Lead Engineer, Adiuvo Engineering & Training Ltd</strong></td></tr><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;">Adam has over 18 years engineering experience of which a significant number of these are at Design Authority / Responsible Engineer level on complex System and Electronic projects for advanced satellite payloads, safety critical systems (SIL4) and other high performance systems. He is both a Chartered Engineer and Fellow of the IET, as well as, a prolific blogger on technical subjects such as Electronics design, FPGA design and Reliable techniques.He is also the author of the MicroZed Chronicles, a weekly blog which focuses on the Xilinx Zynq & Zynq UltraScale+ SoC, as well as, the Vivado and SDSoC tool sets. The series contains over 250 in depth technical articles, providing examples and how to's which cover every aspect of using the device from basics to advanced concepts such as Asymmetric Multi Processing and High Level Synthesis.</td></tr></tbody></table> <div class="migration-injected-attachments"><div style="font-weight:bold;margin:15px 0 5px 0;">Attachments:</div><div></div><table style="border:0;"><tbody><tr><td width="160"><span class="_se_attachment" id="attid_https://www.element14.com/community/api/core/v3/attachments/306439"><span class="ui-webpreview" data-configuration="url=https%3A%2F%2Fcommunity-storage.element14.com%2Ftelligent-evolution-extensions-calendar-calendarfiles%2F00%2F00%2F00%2F00%2F71%2FWorking_With_Vivado_P1.pdf%3Fsv%3D2016-05-31%26amp%3Bsr%3Db%26amp%3Bsig%3DYWhqTeNiyrgHasdc%252FbijM2J0ZCcON9JZa%252FcuCfE2rmk%253D%26amp%3Bse%3D2021-10-17T23%253A59%253A59Z%26amp%3Bsp%3Dr%26amp%3B_%3DZVPU%2FyEcTyAaMeEJJXz0iQ%3D%3D"><img loading="lazy" src="https://community-storage.element14.com/communityserver-components-imagefileviewer/filetypeimages/pdf.png-15x200.png?_=7grsSdvE9pYU/tGMtWz/9g==" border="0" alt="" style="max-height: 200px;max-width: 15px;" /></span></span></td><td><span style="font-size:80%;">Working_With_Vivado_P1.pdf</span></td></tr></tbody></table></div>en-USTelligent Community 12https://community.element14.com/learn/events/c/e/1454Wed, 19 Aug 2020 20:20:46 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:79a0d4e6-dee9-4010-acbb-56f863de499fadamtaylorcengfiet<p>Please remember to download and install Vivado 2020.1 prior to the lab series starting </p><p> </p><p><a class="jive-link-external-small" href="https://www.xilinx.com/support/download.html" rel="nofollow ugc noopener" target="_blank">https://www.xilinx.com/support/download.html</a></p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Fri, 21 Aug 2020 01:00:22 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1367f9a4-8b83-4182-a5d2-21128f4d1516saadtiwana_int<p>Can't miss a webinar by Adam Taylor!! <span><a href="https://community.element14.com/resized-image/__size/16x16/__key/commentfiles/07eef79e70814fd2b5486cddd02e66b1-facb3259-e981-431d-bdc7-67d7c1cb8293/contentimage_5F00_1.png"><img alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/commentfiles/07eef79e70814fd2b5486cddd02e66b1/facb3259/e981/431d/bdc7/67d7c1cb8293/contentimage_1.png-16x16.png?sv=2016-05-31&sr=b&sig=9SnUM3yo1WEBsfyKLhFOw9FMdtZ%2BU%2BSzwiClNwMEwvw%3D&se=2026-06-06T23%3A59%3A59Z&sp=r&_=zGEM7pHL10Vt71gae75OdA==" style="max-height: 16px;max-width: 16px;" /></a></span> (Thanks!)</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Sun, 23 Aug 2020 11:34:50 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9ea11b40-7297-4597-80c9-3f36f3d666a2electronbyelectron<p>Will the session be recorded?</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Tue, 25 Aug 2020 10:56:19 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d974310-c693-4df0-b7c0-f1ad7d5b68e9adamtaylorcengfiet<p>You can get the lab book and initial files from my github </p><p><a class="jive-link-external-small" href="https://github.com/ATaylorCEngFIET/Getting-to-Know-Vivado/tree/master/LabOne" rel="nofollow ugc noopener" target="_blank">https://github.com/ATaylorCEngFIET/Getting-to-Know-Vivado/tree/master/LabOne</a></p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Tue, 25 Aug 2020 14:21:39 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d6cb5c6f-8ff9-4b0a-85d4-a9f779af81eaharishsirah<p>Mr. Adam Taylor, If possible make the sessions recorded and provide to us since participants are from different time zones. It is some what less comfortable to attend these valuable sessions.</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Thu, 27 Aug 2020 08:08:24 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:11e00a0e-39a6-42c8-b28d-2f6452c85dd6javagoza<p>Thanks, Adam, the lab is fantastic.</p><p>I love the rhythm you take, there is no time to get bored and you can follow the lab very well.</p><p>I was lazy to start with FPGA development, but I think it will completely hook me.</p><p>Great job!</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Thu, 27 Aug 2020 12:05:41 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:17fc9db4-d56a-49ad-84c6-c182393a3d78daemoninformatica<p>As a FPGA 'noob' (as in no practical experience, just a lot of theoretical knowledge), I found the first presentation beautifully easy to follow indeed. </p><p> </p><p>One of the things I loved most about the presentation was the part where it was shown how the implementation step actually routed and placed the logic blocks on the surface of fhe fabric. =)</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Tue, 08 Sep 2020 23:03:15 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:57283deb-5e08-4f86-b0b6-adbd7201fce7simlastik<p>Fantastic!</p><div style="clear:both;"></div>https://community.element14.com/learn/events/c/e/1454Sat, 12 Sep 2020 22:50:53 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f35e8cb4-6870-4487-9e8e-aef8e5d9ebd6jalilhel82<p>Can this workshop be completed using Vivado 2019.1?</p><p> </p><p>Please advise.</p><p> </p><p>Gratitude!</p><div style="clear:both;"></div>