https://community.element14.com/learn/events/c/e/1456<p style="margin:0;"><span><a href="https://community.element14.com/resized-image/__size/289x144/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142677.png"><img alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142677.png-289x144.png?sv=2016-05-31&sr=b&sig=csiejsalq4Q%2FlLi5460uw3Ul6ie8%2FYLz6BPH3tFIYbQ%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=BzPFW6NCZwsUb4nuUSCThg==" style="max-height: 144px;max-width: 289px;" /></a></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><em>The Vivado Design Suite from Xilinx offers tools and methodologies to speed up FPGA development, while improving productivity. Within Vivado, developers can leverage C-based design, capture, simulate and implement programmable logic designs targeting Xilinx FPGA and SoCs (System-on-Chips).</em></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">This three-session introduction to Xilinx Vivado Design Suite will examine how we capture designs in Vivado using both RTL entry and IP Integrator. Following design capture we will examine Vivado’s simulation capabilities that help ensure the performance of the captured design aligns with requirements. When we reach the desired functional performance level, we will move on to design implementation and programming file creation for deployment.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span><a href="https://community.element14.com/resized-image/__size/527x172/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142678.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142678.jpg-527x172.jpg?sv=2016-05-31&sr=b&sig=WiMMdiuNAvCX%2Fv0tbt23MjA%2BWaSR7MRRN6nUeLtnbyk%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=PDt3vgtA64iDCx3GqygPDQ==" style="max-height: 172px;max-width: 527px;" /></a></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>To participate <a class="jive-link-external-small" href="https://www.xilinx.com/support/download.html" rel="nofollow ugc noopener" target="_blank">download Vivado 2020.1</a> and download the attached lab book below!   You can also download the lab book <a class="jive-link-external-small" href="https://github.com/ATaylorCEngFIET/Getting-to-Know-Vivado" rel="nofollow ugc noopener" target="_blank">here</a>!</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">Just as with real life, our journey does not end there. We will also explore how we can debug the implemented design on the device as it is integrated into the wider system, should the need occur.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">Each workshop session will walk you through everything you need to know to go from a Zero to a Hero using Vivado.  Adam Taylor will walk you through everything you need to know to get started using Vivado.  Like the previous PYNQ course we will provide examples, and as the series progresses build onto what we've learned.  No board is required.</p><p style="margin:0;padding:0px;"> </p><h2><span style="color:#3334ca;">Session 3:</span></h2><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will introduce advanced concepts, such as creating our own custom IPs, debugging on hardware, working with configuration control, and scripting in Vivado.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>Creating custom IP using AXI interfaces</li><li>Debugging in Vivado – ILA, VIO insertion</li><li>Working with softcore processors – MicroBlaze example</li><li>Configuration control and scripting</li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span><a href="https://community.element14.com/resized-image/__size/387x261/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142679.gif"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142679.gif-387x261.png?sv=2016-05-31&sr=b&sig=GfxeGJWjeGbUg2zM7Yi8JZQZ8oOv3WLFIuIWJzUyA6Q%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=bMfKL3GLOoTwlyJflfldXQ==" style="max-height: 261px;max-width: 387px;" /></a></span></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><span style="color:#333333;font-family:Arial, 'Lucida Grande', sans-serif;font-size:16px;font-weight:bold;">Dates and Register for Free:</span></p><p style="margin:0;padding:0px;"> </p><table border="1" class="jiveBorder mce-item-table" style="border:1px solid #c6c6c6;width:100%;"><thead><tr><th style="border:1px solid black;border:1px solid #c6c6c6;padding:6px;color:#505050;background-color:#f2f2f2;text-align:left;" valign="middle"><strong>Workshop:</strong></th><th style="border:1px solid black;border:1px solid #c6c6c6;padding:6px;color:#505050;background-color:#f2f2f2;text-align:left;" valign="middle"><span style="color:#505050;"><strong>Dates and Time:</strong></span></th></tr></thead><tbody><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><a name="workshops"></a><p style="margin:0;"><strong>Session 1 - Getting to Know Vivado Pt 1</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream</li><li>What do we use Vivado for? What is its role in FPGA and SoC Development?</li><li>Design entry in Vivado -> RTL View</li><li>Simulation -> XSIM (Vivado RTL Simulation)</li><li>Implementation Flow -> Synthesis View, Implementation, Bit Stream</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 26th of August 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><strong><a class="jive-link-event" href="https://www.element14.com/community/events/5605/l/xilinx-workshop-getting-to-know-vivado-part-i">Xilinx Workshop: Getting to Know Vivado Part I</a></strong></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/313x176/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142680.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142680.jpg-313x176.jpg?sv=2016-05-31&sr=b&sig=uw5Q4nxwc3AeHY3X1Wj8YRvDrbSXodA5t0s6W8aNopY%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=Nq0FuVZ2awedy2iFsWrIOQ==" style="max-height: 176px;max-width: 313px;" /></a></span></strong></p></td></tr><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Session 2 - Getting to Know Vivado - Part II</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will look more closely at more commonly used features which enable designs to be generated faster.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>IP Integrator – Reduce the RTL you need to write and accelerate your design</li><li>Constraints – What is there role in the design, how do we use them?</li><li>Timing Analysis – What is timing closure, why is it important, and how do we achieve it?</li><li>Programming Configuration Memories</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 2nd of Sept 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><strong><a class="jive-link-event" href="https://www.element14.com/community/events/5612/l/xilinx-workshop-getting-to-know-vivado-part-ii">Xilinx Workshop: Getting to Know Vivado Part II</a></strong></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/312x175/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142681.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142681.jpg-312x175.jpg?sv=2016-05-31&sr=b&sig=IGQDq1O1por5g5bhCzJE4K5IhpALCMwGcZRaMWmYU%2F8%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=CbdgtGNli00ccHsb34D5pA==" style="max-height: 175px;max-width: 312px;" /></a></span></strong></p></td></tr><tr><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Session 3 - Getting to Know Vivado - Part III</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;">In this session we will introduce advanced concepts, such as creating our own custom IPs, debugging on hardware, working with configuration control, and scripting in Vivado.</p><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong>Topics covered include:</strong></p><p style="margin:0;padding:0px;"> </p><ul><li>Creating custom IP using AXI interfaces</li><li>Debugging in Vivado – ILA, VIO insertion</li><li>Working with softcore processors – MicroBlaze example</li><li>Configuration control and scripting</li></ul></td><td style="border:1px solid black;border:1px solid #c6c6c6;width:50%;padding:6px;"><p style="margin:0;"><strong>Wednesday, 9th of Sept 2020</strong></p><p style="margin:0;padding:0px;"> </p><p style="margin:0;font-family:Arial, 'Lucida Grande', sans-serif;color:#333333;"><span style="font-weight:bold;font-style:inherit;font-family:inherit;">10:30 CT / 3:30 PM GMT</span></p><p style="margin:0;padding:0px;"> </p><ul><li><span style="color:#e23d39;"><strong>Register Above for Free!</strong></span></li></ul><p style="margin:0;padding:0px;"> </p><p style="margin:0;"><strong><span><a href="https://community.element14.com/resized-image/__size/314x176/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142682.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142682.jpg-314x176.jpg?sv=2016-05-31&sr=b&sig=5dzYnoVOkuTV9ZrgHXFEIuTYPTw0CXFIvU%2F4eJ1VDf0%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=APd3Q0Z8IQOEQrs2l80t8Q==" style="max-height: 176px;max-width: 314px;" /></a></span></strong></p></td></tr></tbody></table><p style="margin:0;padding:0px;"> </p><h2><span style="color:#3334ca;">Presenter:</span></h2><p style="margin:0;padding:0px;"> </p><table border="1" class="jiveBorder mce-item-table" height="326" style="border:1px solid #ffffff;width:100%;height:265px;"><tbody><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;"><span><a href="https://community.element14.com/resized-image/__size/138x138/__key/telligent-evolution-extensions-calendar-calendarfiles/00-00-00-00-71/contentimage_5F00_142683.jpg"><img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/telligent/evolution/extensions/calendar/calendarfiles/00/00/00/00/71/contentimage_142683.jpg-138x138.jpg?sv=2016-05-31&sr=b&sig=aVHbLpSxEhkULWzupIOm3Xz96H180bEsXen09s3M7Hw%3D&se=2026-04-12T23%3A59%3A59Z&sp=r&_=vrBDDDmPKqcq/LfhEaAOpg==" style="max-height: 138px;max-width: 138px;" /></a></span></td></tr><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;"><strong>Founder and Lead Engineer, Adiuvo Engineering & Training Ltd</strong></td></tr><tr><td style="border:1px solid black;border:1px solid #ffffff;padding:6px;">Adam has over 18 years engineering experience of which a significant number of these are at Design Authority / Responsible Engineer level on complex System and Electronic projects for advanced satellite payloads, safety critical systems (SIL4) and other high performance systems. He is both a Chartered Engineer and Fellow of the IET, as well as, a prolific blogger on technical subjects such as Electronics design, FPGA design and Reliable techniques.He is also the author of the MicroZed Chronicles, a weekly blog which focuses on the Xilinx Zynq & Zynq UltraScale+ SoC, as well as, the Vivado and SDSoC tool sets. The series contains over 250 in depth technical articles, providing examples and how to's which cover every aspect of using the device from basics to advanced concepts such as Asymmetric Multi Processing and High Level Synthesis.</td></tr></tbody></table> <div class="migration-injected-attachments"><div style="font-weight:bold;margin:15px 0 5px 0;">Attachments:</div><div></div><table style="border:0;"><tbody><tr><td width="160"><span class="_se_attachment" id="attid_https://www.element14.com/community/api/core/v3/attachments/306961"><span class="ui-webpreview" data-configuration="url=https%3A%2F%2Fcommunity-storage.element14.com%2Ftelligent-evolution-extensions-calendar-calendarfiles%2F00%2F00%2F00%2F00%2F71%2FWorking_With_Vivado_P3.pdf%3Fsv%3D2016-05-31%26amp%3Bsr%3Db%26amp%3Bsig%3D8T3tQIaZRGpgnPBFKDbY0pJ9%252B5QmxBA9X8jsyNLbJ%252BQ%253D%26amp%3Bse%3D2021-10-17T23%253A59%253A59Z%26amp%3Bsp%3Dr%26amp%3B_%3DX%2FsGixOQitGFQ3Q%2By0RlWg%3D%3D"><img loading="lazy" src="https://community-storage.element14.com/communityserver-components-imagefileviewer/filetypeimages/pdf.png-15x200.png?_=7grsSdvE9pYU/tGMtWz/9g==" border="0" alt="" style="max-height: 200px;max-width: 15px;" /></span></span></td><td><span style="font-size:80%;">Working_With_Vivado_P3.pdf</span></td></tr></tbody></table></div>en-USTelligent Community 12https://community.element14.com/learn/events/c/e/1456Wed, 09 Sep 2020 14:36:23 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:56b9e325-d22f-49ac-8530-e638c8a2e44fbuffteethr<p>Good Morning. I was hoping the you would cover Microblaze as well as mentioned in the description.</p><div style="clear:both;"></div>