Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor

re: Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor by Jan Cumps

Jan Cumps — Thu, 12 Aug 2021 19:03:49 GMT

If there is room for an out-of-curriculum request: please demo a simulation/test-bench exercise in Vivado.

It's a selfish request. I have experience with simulation in ISE/Spartan. Struggling with the Zynq style packages that combine processor and fabric.

re: Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor by dc73

dc73 — Sun, 15 Aug 2021 22:14:26 GMT

I thought I'd share a tip that helped me out with learning the Vivado->Vitis export-import system as I come from the Vivado->SDK work as of 2-1/2 years ago and have been relearning the system. So, I hope this is not wasting your time. I also want to apologize to Bryan and Avnet for mentioning Digilent in this post, but I find going between the two companies' sites has really helped me. Avnet is a leader in educating customers. Digilent has been a very good source of education as well. Anyway, enough of the disclosures, here's what I learned.

I have Avnet's Micro/MiniZed (along with Zybo and ZedBoards) from about 4 years ago when I was brought on a project that would use the Zynq in a high-reliability program. My primary role was as a C++ software developer, but I also took the time to understand the Fabric (PL) to debug my software. More recently, I was working my way through some Altera FPGA material to learn VHDL/Verilog to prepare myself to teach FPS material, or work remotely for hire. The Ultra Scale workshop came along, and it gave me the motivation to pull out my old hardware, waiting for the next Ultra96 session. My key hangup was learning how to export from Vivado and into Vitis. I got pretty close without reading too much of the manual (it's hard to find the right video/subject on Xilinx's site without paying), and, today I was able to find what I needed.On the Digilent website (www.digilent.com) you can find a great tutorial on just this subject (https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi ) titled This article is a complete project, but you can skip through most of it if you just want to know how to export out of Vivado and into Vitis. The nice thing, however, about the article is they are setting up for using PMODs which I think Brian is about to do. So, I am working through the article with the PMODs in mind on one of my MiniZed boards, saving my Ultra96 for Wednesday as I want to keep in sync with Bryan.

I also wanted to give a shout out to Jan Crmps for asking about simulation. I have used modelsim on Altera's Quartus II product and my final step (after the workshop) will be to bone up on the simulation on the Xilinx platform

So, a bit wordy, I know, but if you want to get a jump on things, this Digilent article help me prepare for Wednesday (I think)

Dave

re: Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor by Andrew J

Andrew J — Wed, 18 Aug 2021 17:08:44 GMT

One of the useful learning resources I've come across is here (Open Hardware Repository): https://ohwr.org/project/soc-course/wikis/home

Someone was asking in this workshop about debugging and this is covered at a high level during the sessions on the OHWR as you progress. At one point, you will reach an example that has you build an application targeted at the A53 and an application targeted at the R5 that will both run simultaneously and 'talk' to each other. It provides the source code and initial steps, but doesn't explain how to build, deploy and debug this; if you followed the earlier sessions you can figure it out. At least I did and I can I expect others to be able to as well, I'm no genius!! As a means of getting to grips with the debugger and debug configurations it's pretty good and doesn't drop you in the deep end.

re: Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor by Andrew J

Andrew J — Thu, 19 Aug 2021 19:26:05 GMT

bhfletcher

Hi Bryan, I wanted to send you a message re: peripherals test but the system won’t allow me to do so: I thought by following you and you accepting would resolve that, but apparently not. I didn’t want to ask it directly here as any answer may give away what you are asking people to investigate. Is there any additional info you can give about what you mean by ‘it will hang at some point’ without giving the game away?

re: Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor by bhfletcher

bhfletcher — Wed, 01 Sep 2021 04:12:32 GMT

Regarding the homework for Workshop #3 to create and run the Peripherals Test, I have created a blog to walk you through those steps.

Ultra96-V2 Workshop Homework: Peripherals Test

This also explains the error that I expected you to see with the self-test of the PS UART 0 (attached to the Bluetooth), except that the error never happens because it is no longer an error in 2021.1!

Bryan