Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by Aniket_kumar_raj

Aniket_kumar_raj — Fri, 13 Mar 2026 16:15:40 GMT

This is going to be my headstart to FPGA development

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by battlecoder

battlecoder — Sun, 22 Mar 2026 06:36:11 GMT

I've only used a very simple FPGA platform in the past, and did very little with it beyond testing a "hello world"-like demo (I think it was an LED blinker). I've always found FPGAs to be very fascinating but rather intimidating beasts. I'll try to watch this. It might actually (and finally) get me into FPGAs.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by veluv01

veluv01 — Thu, 26 Mar 2026 14:00:21 GMT

Finally....Ultrascale+ in the Spartan, can't wait to test the performance of it.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by Eamon

Eamon — Thu, 26 Mar 2026 14:10:27 GMT

Great seminar topic! Showing more affordable devboards is nice for the maker community and also professionals, where switching FPGAs is more acceptable in the lower end range. Would be interested to see more use cases of the SCU35

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by JWx

JWx — Thu, 26 Mar 2026 14:19:22 GMT

JoRatcliffe webinar quiz re-appears after page reload/in every new tab, so one is unsure if it was already counted or needs to be repeated...

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by fyaocn

fyaocn — Thu, 26 Mar 2026 14:36:35 GMT

Understanding of FPGA needs prerequisite knowledge.

Attached datasheet cover only 2 pages.

Better give more documents about the board and IDEs in advance.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by HectorV

HectorV — Thu, 26 Mar 2026 15:30:13 GMT

Great webinar! The demos look pretty cool. For the price the SCU35 kit seems very powerful.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by pandoramc

pandoramc — Thu, 26 Mar 2026 15:41:40 GMT

For high noisy communication interfaces, is there interfaces for digital communication controllers such as differential drivers?

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by wolfgangfriedrich

wolfgangfriedrich — Thu, 26 Mar 2026 15:47:10 GMT

Very interesting content but the webinar spend about 15 minutes with introduction and marketing information. This is half of the whole webinar presentation time. This felt excessive especially as there are probably mostly technical folks on e14 listen to this.

There was an interesting question in the webinar feed:
As of vivado, what licenses are required? And what commercial IPs are available during the design process.
Users purchasing the kit get 1 year tools license for free (node locked, device locked). All the free IPs available AMD catalog are included

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by AdrianBD

AdrianBD — Thu, 26 Mar 2026 15:48:16 GMT

I'm starting in FPGAs and found this webinars very useful. I would like the webinars to belonger.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by Morris_kit

Morris_kit — Thu, 26 Mar 2026 16:00:18 GMT

Great session ! Perfect starting point to set a launchpad for diving into FPGA development and building projects.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by ldmort123

ldmort123 — Thu, 26 Mar 2026 16:04:12 GMT

It was a great webinar. As a beginner in FPGAs, I found it very useful for understanding this evaluation kit and its potential applications. I’m looking forward to the next webinar!

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by mustapha_belarbi

mustapha_belarbi — Thu, 26 Mar 2026 16:20:56 GMT

Thank you for the webinar. I found it very interesting, especially Example 3 on multi-signal recording, which is very close to what I am currently trying to achieve in my work: a real-time intelligent irrigation system where multiple environmental signals (soil moisture, temperature, flow, etc.) are continuously monitored and used to dynamically adjust irrigation decisions.

At present, I am working with a ZedBoard platform, but I am considering moving to Spartan UltraScale+ to go further, particularly for integrating more advanced AI-based processing.

Example 3 seems highly relevant to this transition. However, I would appreciate some clarification before investing in this solution:

- Would a multi-signal recording architecture be more efficient and scalable on Spartan UltraScale+ compared to a ZedBoard-based implementation?

- From your experience, do you consider Spartan UltraScale+ more suitable for edge-intelligent control systems like mine, especially when integrating real-time decision-making and AI inference?

A more detailed explanation of Example 3 would be extremely valuable for me, particularly to support the transition from classical FPGA designs to AI-enabled embedded systems.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by veluv01

veluv01 — Thu, 26 Mar 2026 16:42:25 GMT

Thanks for the webinar JoRatcliffe , it was a nice and brief for the info on the SCU35 and the Spartan US+ family FPGAs.Great to hear that the SCU200 will also be coming soon.

Here are my few thoughts,

1.The Q&A felt a bit short. It would be great to have more time for questions.

2.It would be great to see some performance benchmark slides for MicroBlaze V and DSP(maybe...it doesn't matter much since it's a DSP48E2 like in every US+?) performance for the Spartan US+ compared to the Spartan, Artix and Kintex,etc

3. A little more info on the Spartan UltraScale+ specs and architecture, especially the new Platform Management Controller, would help a lot.

4.An unboxing video of the kit would be a really nice addition for a getting started webinar!

I hope that there will be a webinar for the SCU200 too, since it would be really interesting to see what the Spartan UltraScale+ can all offer and what it's capable of.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by chloro

chloro — Thu, 26 Mar 2026 17:26:32 GMT

The examples were good, especially the different approaches like using MicroBlaze with Zephyr and implementing it all in the hardware. This helped me understand how the board can be used in different ways depending on the application.

One thing that I thought of while going through the presentation is that it would have helped if there were demonstrations of how the different interfaces on the board can be used in combination in one single setup, rather than the different demos. This is because the board has quite a few I/O interfaces, and understanding how to use them all in combination would have helped.

Also, maybe a little more information on how to handle the high-speed I/O interfaces, as this seemed like one of the major advantages of the board, although this aspect was not discussed in great detail.

Overall it was easy to follow and gave a good idea of what the board can be used for.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by jelektro

jelektro — Thu, 26 Mar 2026 17:52:59 GMT

The webinar was conducted in an accessible way and was technically sound. However, I would like to see more examples, preferably with the creation of each project presented from start to finish.

The second design example (SCU35 Data Acquisition) is very interesting. In future webinars, it would be great to see methods for connecting to a PC via high-speed communication interfaces such as USB3 or Gigabit Ethernet. The SCU35 would be an excellent choice as a control unit for high-speed logic analyzers or mixed-signal oscilloscopes. Unfortunately, the board does not include a built-in USB-FIFO interface, such as USB3 or USB2 High-Speed. It’s also a pity that a Gigabit Ethernet transceiver was not used.

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by wstod

wstod — Fri, 27 Mar 2026 16:34:34 GMT

Is it possible the developer path other than emulating classic CPU via softcore and RTOS overhead to use AI models via inference engines (interpreters) which omits FPGA advantages (parallel processing) over classic CPU architecture? For example generating directly cell fabric logic in VHDL or Verilog directly from High Level Languages as well from AI models?

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by JoRatcliffe

JoRatcliffe — Wed, 15 Apr 2026 14:39:39 GMT

A big congrats to the winners of this webinar's contest!

Very well done on speedily scoring 100% in the quiz in addition to watching the webinar and sending in your questions and comments. E14Alice will be in touch to discuss shipping the prizes

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by Humaninsane

Humaninsane — Thu, 16 Apr 2026 02:31:30 GMT

you guys received the FPGA kit??

re: Getting Started with the AMD Spartan™︎ UltraScale+™︎ FPGA SCU35 Eval Kit by JoRatcliffe

JoRatcliffe — Mon, 20 Apr 2026 14:39:18 GMT

The AMD team have shared their answers with me to the questions we were not able to answer live during this webinar's Q&A so I am including all of them below. Thanks again to everyone that submitted a question during this webinar's Q&A!

Q: When using a MicroBlaze softcore, is there a metric measured in mW/MHz to evaluate if it makes sense to move calculations from the softcore/firmware in the FPGA fabric/logic processing?
A: This would need to be done experimentally on a per design basis. There are too many variables to make metrics like this unfortunately.

Q: What percentage of FPGA resources are used when MicroBlaze processor is deployed?
A: In UG1629 we have metrics on the fmax and resources utilization of some preconfigured MicroBlaze V designs. In 2025.2, for SCU35, we can see a microcontroller design is expected to use 2175 LUTs (2175/16000 ~= 14%) and 1135 FFs (1135/33000 ~= 4%). Note that the numbers in UG1629 are just for the processor, addition resources would be needed for peripherals, this are generally much smaller than the processor though.

Q: Is there any software for this kit in the hobbyist price range that can be used when 1 year license expires?
A: The SU35P device on the SCU35 board is supported in the free Vivado Basic, which can be renewed each year for free.

Q: Do you plan the development path other than emulating classic CPU via softcore and RTOS overhead to use AI models via inference engines (interpreters) which omits FPGA advantages (parallel processing) over classic CPU architecture? For example generating directly cell fabric logic in VHDL or Verilog directly from High Level Languages as well from AI models?
A: This is possible today with 3^rd party tools like https://www.mathworks.com/help/deep-learning-hdl/xilinxfpgaandsocdevices.html, https://opensource.web.cern.ch/HLS4ML, and https://www.makarenalabs.com/h4z/.

Q: How's the improvement in performance for Microblaze V deployed in the Spartan US+ when compared to the Spartan and Artix?
A: Using the numbers in UG1629 we can compare the Fmax of MicroBlaze V in various FPGA families. We don’t expect a huge performance difference amongst the various devices in the same family as they all use the same silicon technology.

Q: The SCU200 kit looks like it can be plugged into a PC
A: SCU200 will support PCIex4 gen4 and can be plugged into a PC. The card is not intended to be used in a permanent installation as does not fit all the PCIe mechanical standards (eg. it is too high for a case lid to be closed).

Q: How does power draw compare to past Spartan generations and other lower-cost options?
A: The SU+ listicle provides excellent insight into this question. https://www.amd.com/content/dam/amd/en/documents/products/adaptive-socs-and-fpgas/fpga/ultrascale-plus/5-reasons-to-choose-spartan-ultrascale-plus-listicle.pdf

The proven 16 nm architecture offers significant power savings—projected to offer up to a 30% reduction in total power compared to the previous 28 nm series on lower densities —while delivering up to 1.9X fabric performance. For applications requiring high-performance interfaces like LPDDR4x/LPDDR5 memory or PCIe® Gen4, the larger Spartan UltraScale+ FPGAs also include hardened IP, projected to improve overall power efficiency up to 60% and enhance overall system performance.

The best way to determine power savings is to compare real application scenarios in Power Design Manager for each architecture you are considering.

Q: As a hobbyist new to FPGAs, I noticed the SU35P on the SCU35 has 48 DSP slices and 48 Block RAMs. Does the kit’s architecture allow efficient use of these built-in resources for real-time processing tasks like sensor filtering or PWM generation?
A: Yes, the architecture is designed for efficient interaction between DSP and BlockRAM. I recommend the UltraFast Design Guide and speaking with your local FAE.

Q: And how should a complete beginner approach utilizing the DSP slices and Block RAM without overcomplicating the design — for example, starting with ready-made IPs in Vivado or combining them with the MicroBlaze V processor?
A: There is not a single answer to this question. For background, I recommend reading this section in the UltraFast Design Methodology Guide: https://docs.amd.com/r/2020.2-English/ug949-vivado-design-methodology/Know-What-You-Infer

Referring to existing example designs that have been published is also a good way to start. For example: https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447

Q: The Platform Management Controller is interesting addition to the Spartan US+, will it be available in the other families too? It kinda seems interesting to me for the over the air updates and remote management.
A: The platform management controller processor is not available for customer use. Some of the peripherals in the platform management controller are available to customers. There are some details in UG860.

Q: For a multi-sensor edge system on SCU35 using MicroBlaze + HyperRAM, what are the main throughput and latency bottlenecks, and how does the current IP/tool support limit optimization?
A: The main throughput and latency bottleneck in most systems is memory bandwidth. This is also the case here. The HyperRAM is connected via QSPI which is not a high speed interface, it runs at max 200MHz. A larger Spartan UltraScale+ device would be capable of using a DDR4 soft memory controller or LPDDR4/4x/5/5x hardened memory controller that will give several Gbps of memory bandwidth and much lower latency.

Q: Is the kit free?
A: The kit details at: https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/scu35.html

Price: $229.00
Part Number: EK-SCU35-G

However, if you are a content creator interested in producing trainings or example designs, please contact us!

Q: Do you have any examples connected with local AI processing?
A: The Spartan UltraScale+ FPGAs and their Evaluation kits are not ideal for AI processing uses cases, our portfolio of adaptive SoCs product (Versal and Zynq UltraScale+ MPSoC) are better suited. We do envision a use case where the Spartan UltraScale+ FPGA can be used to gather real-time data through multiple sensors and feed them to an adaptive SoC or x86 Embedded Ryzen APU on the same board for local AI processing.