NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by gecoz

gecoz — Fri, 17 Nov 2017 16:09:30 GMT

Excellent presentation, thank you!

Fabio.

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by bm010

bm010 — Fri, 17 Nov 2017 16:14:42 GMT

Thanks, learned a lot today.

Nick said during the webinar I should post here to get pointers to more information on the question:

What are best practices for Zynq PS+PL debugging? particularly best practice for generating AXI commands for the Zynq VIP and using cross triggers

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by rscasny

rscasny — Fri, 17 Nov 2017 16:25:28 GMT

Questions asked during the webinar:

Do you have a glossary that explains all of the FPGA specific terms you are using?

Do you have embedded security features on the chip?

Can the I/O pins work without any interaction with the software on the main processor?

How complex can the FPGA circuits be on this board. ie transistor equivalent configuration.

What is the SDSoC License?

How would you compare this board to the Cypress Semiconductor PSOC 5 board?

What tradeoffs should I think about when choosing between AXI ACP vs DMA to communicate data to an accelerator in the PL?

I see a link to Mathworks, what is in the Mathworks design package? (Coppersmith)

Does the board have a Python implementation?

Does the board work with OpenCV?

Is there a cryptographic module on Zynq SoCs (or are there any designs available to implement in the programmable logic part)?

What will you be using the I2C and UART for in this case?

Is there any plan to make minized with larger Zynq devices (in terms of logic cells)? (martin simlastick)

The Vivado seems very simplistic, how large of a learning curve is there to become proficient in using the software?

Can we use PL part with Linux?

When verifying a Zynq design with the Zynq VIP, is there a best practice for generating AXI commands from your application code?

I'm new to Vivado. What simulation environment is used with SDSoC? Is it like ModelSim? Or is some of the programmable logic simulation done in the SDK?

Does this board support U-boot, Yocto project and QT Framework stack?

Are Xilinx planning to run any free training days like in a roadshow in different cities worldwide? It may be worthwhile, to get developers up-to-speed with this platform and Vivado and SDSoc.

Who manages the AXI address space when you add multiple IP to the buses? Is this Vivado automatically or can we assign it manually?

Do we need to manually generate the DTB for Linux ? Is it done automatically or manually?

MiniZED: Any other General-purpose pins connected to PL in addition to the PMOD and Arduino Headers?

Vivado Suite (webpack): does it degrade simulation like ISE with large designs?

MiniZED: What's power consumption (average?)

How does this compare to the ZedBoard for educational purposes? Would you recommend this to a person new to FPGA development?

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by rscasny

rscasny — Fri, 17 Nov 2017 16:43:42 GMT

I asked the presenter to select the top 3 questions. Here they are:

What tradeoffs should I think about when choosing between AXI ACP vs DMA to communicate data to an accelerator in the PL? Brandon Myers bm010

I see a link to Mathworks, what is in the Mathworks design package? R. Scott Coppersmith rsc

Who manages the AXI address space when you add multiple IP to the buses? Is this Vivado automatically or can we assign it manually? Ãlvaro Lopes alvieboy

I need your mailing addresses with phone and emails. message me at rscasny with the info.

Randall

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by rsc

rsc — Fri, 17 Nov 2017 19:24:08 GMT

The webinar was well done, however, since I'm not familiar with Zynq, some of the topics and abbreviations I didn't understand.

I'll ask around to see if we use it in our EE/CS classes here, I know they use Xilinx ISE Design Suite in several classes.

if so, I'll suggest the instructors have their motivated students apply to roadtest this part.

Scott

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by joaoflou

joaoflou — Sun, 19 Nov 2017 17:52:12 GMT

Will you make the recording available? I would appreciate it, since I didn't manage to get the conference application running.

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by rscasny

rscasny — Mon, 20 Nov 2017 16:47:39 GMT

We are shipping The Zynq Book to the winners today:

alvieboy

rsc

bm010

re: NEW!: Let's Get Started with the Zynq 7000 Using the AVNET MiniZed Dev Board by rscasny

rscasny — Mon, 20 Nov 2017 18:28:37 GMT

The webinar recording is now posted.