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Nanowire transistors go vertical

Catwell

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Two metal gates providing dual transistors on a single nanowire (via IEEE)

 

Moore's law rears its validity once more. Xiang Li and a team of researchers from A*STAR have created a vertical transistor using nanowires. Although 3D transistors is not a new idea, through the use of a nanowire as a center mount for two wrap around gates, a transistor has been designed that will reduce the transistor size by a factor of two. Reducing the area will allow silicon designs to be much more compact and dense as predicted by Moore's law.

 

 

The design used to create the vertical transistors consisted of a center cylinder made from the nanowire and two transistors stacked on top of each other separated by a dielectric. Along with reducing size, the technique also allows the transistors to control the current on each gate independently. In addition, the voltage applied to one of the vertical transistors does not affect the threshold voltage of the other, unlike other independent double-gate transistor designs. In other words, activate one gate, but not the other.

 

 

Furthermore, scientist hope that the emerging transistor design may soon be integrated with tunnel field effect transistors (TFETs). The combination of the two would create a product that will consume much less power due to TFETs relying upon the tunneling of electrons rather than thermal activation of electrons. The new vertical transistors will have many useful applications including non-volatile memory, logic gates, and may help save energy by creating better, cheaper and lower-powered processors. See more about the project after this link.

 

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