[jc2048] Staircase Generator

RE: [jc2048] Staircase Generator

Pelorito1993 — Mon, 11 Jul 2022 03:09:12 GMT

The circuit is extremely simple and inexpensive compared to ladder generators made with binary counters and gates. It may not have a lot of precision but in some applications precision is not so necessary.
It could be used to plot semiconductor characteristics as the old Tektronix 370 did.
Each step jump could be an "Ib" of a transistor for example.
I think the development would be more complete if you included two important things.
a) The possibility to determine the number of steps you want. For example, you could place a reference voltage and a comparator. When the ladder reaches that reference voltage, it triggers a pulse that resets the ladder making it start again.
If you can make the height of each step equal to the input voltage, you could even have an analog counter.
If you know that your input voltage is - for example - 100 mV, and you set your reset voltage to 10 Volts, then you know that if the ladder has reset it means that 100 steps were generated. To achieve this, you need the height of each step to be exactly at the voltage you set at the input. This way you would have a tension variable staircase. (voltage Variable Staircase or VVS)
This so designed can be used to make a step generator where with a key you can choose how many steps you want the signal to have .....
These are all ideas that can be developed.
A friendly greeting from Argentina

RE: [jc2048] Staircase Generator

dougw — Mon, 29 Nov 2021 15:11:20 GMT

Your circuit would also lent itself to making a smooth sawtooth wave by using a small pump cap (small step size) and a lot of steps.

Pretty versatile circuit.

RE: [jc2048] Staircase Generator

dougw — Sun, 28 Nov 2021 19:45:40 GMT

Ultra cool circuit. I would have guessed an R2R DAC using a CPLD counter.

Your circuit has the ability to generate much higher voltages than the digital logic supply would suggest, although you might need an extra transistor to get there.

RE: [jc2048] Staircase Generator

michaelkellett — Sun, 28 Nov 2021 17:23:12 GMT

Hello, nice to see some HDL for simple parts !

Here's a style thing that might help when you do state machines:

You can replace:

constant STEP_X_STATE : std_logic_vector(1 downto 0) := "10";
constant PAUSE_X_STATE : std_logic_vector(1 downto 0) := "01";
constant RESET_X_STATE : std_logic_vector(1 downto 0) := "00";

with something like:

TYPE t_x_state is (STEP_X_STATE , PAUSE_X_STATE , RESET_X_STATE );
signal x_state : t_x_state;

and then in the case statement:

                case x_state is
                   when STEP_X_STATE =>
                     --do stuff

more cases

                    when others =>

                       -- handle it all going wrong
               end case;

Where it really pays off is when you want to add a state and go from maybe 4 bits to 5 bits, you don't need to edit all those "00110! again.

RE: [jc2048] Staircase Generator

shabaz — Sun, 28 Nov 2021 15:22:37 GMT

Hi Jon,

That's very neat, I thought it was from a DAC, but this is more interesting. Perhaps use-cases are low-cost ways to measure unknown capacitance, by number of pulses to charge to a threshold, or even low-current or low-energy measurements, by seeing how many top-up pulses are needed, I think TI's microcontroller dev-boards have a similar concept (EnergyTrace+ or something) although maybe that's implemented differently.

RE: [jc2048] Staircase Generator

Jan Cumps — Sat, 27 Nov 2021 22:49:42 GMT

A question about the 68n capacitor: did you choose it to be large enough to hold 10 charges of the 2.2n one, or is it chosen for a particular time constant?

RE: [jc2048] Staircase Generator

Jan Cumps — Sat, 27 Nov 2021 21:55:26 GMT

The FPGA design works like a charm.

Running it on Xilinx Zynq. Clock also 50 MHz.

RE: [jc2048] Staircase Generator

Jan Cumps — Sat, 27 Nov 2021 20:15:33 GMT

I can't work out how to format as code and all the white space disappeared when I cut and pasted it.

You will get a dialog where you can paste your code into; and select the programming language (not VHDL though - I choose TEXT when inserting that)

RE: [jc2048] Staircase Generator

DAB — Sat, 27 Nov 2021 18:43:39 GMT

It has been a long while since I did any transistor work.

Well done.

RE: [jc2048] Staircase Generator

genebren — Sat, 27 Nov 2021 18:22:12 GMT

Very cool project/blog! I really like the simplicity/elegance of your approach to this project. Nice example of using a CPLD to generate a programmable pulse sequence. Well done!