While working on PCB bring-up for a project of mine recently, I ran across a rather sticky problem: I had neglected to add AC coupling capacitors between the outputs of a single-rail supply audio codec and the inputs of a split-rail supply output amplification stage. The particulars of the PCB made the prospect of adding AC coupling capacitors particularly unpalatable, so I elected to try a different approach. The output stage in question was a non-inverting op-amp based amplifier, diagrammed below.
The gain of this circuit from V_in to V_out is (1 + R2/R1)*(1/sR2C1). C1 is present for high-frequency stability; it limits the gain of the stage to unity at very high frequency. In most cases, V_REF is tied to ground, but it does not have to be. By superposition, the total DC term present at the output is the linear combination of the DC terms present at V_in and V_REF, gained up appropriately. Any DC term present at the input (from a codec output bias, say) will be boosted by the non-inverting amplifier gain factor (1 + R2/R1). The DC term at V_REF will be boosted by the inverting op-amp formula, -(R2/R1). The overall DC present at the output from both inputs becomes V_out,DC = (1 + R2/R1)*V_in,DC - (R2/R1)*V_REF. On the project in the post I linked to above, I was constrained to setting V_REF = V_in,DC, which leads to V_out, DC = (1 + R2/R1)*V_in,DC - (R2/R1)*V_in,DC = V_in,DC.
If we rearrange the formula above a little bit by setting V_out,DC = 0 (corresponding to no DC bias at the amplifier output), we arrive at the following: V_REF = (1 + R1/R2)*V_in,DC. This formula matches the form of the non-inverting op-amp gain stage, suggesting a rather elegant solution to the problem of DC offset:
In the above diagram, R1 = R3, R2 = R4, and V_REF is the DC reference present at V_in. When these conditions are met, the DC bias at V_out should be zero. I built a breadboard prototype of this circuit around an NE5532 op-amp driven by the outputs of a MAX98090 codec, shown below.
While the circuit did successfully reduce the DC bias from about 1.25V at the input to about 40mV at the output, it did not completely remove the bias as desired. Probing the output node of U1 revealed the issue: the DC voltage at the output was slightly too high due to passive component tolerances. I made a simple modification to the design to correct this issue:
R5 is a trim pot added to the ground leg of the feedback network for the DC offset amplifier. Adding it in this location does not affect the placement of the stability pole of the amplifier when the trim pot is adjusted. R5 + R1 should be roughly equal in value to R3. The results with the trim control in place were decidedly better:
My experiments were limited to the parts and tools I had on-hand, and still the results were very encouraging. With a multi-turn and/or small value trim pot (I was using a 270-deg 1k pot) and a precision DMM (i.e. 6.5-digit resolution, as opposed to the 3.5-digit meters I own), I think that this circuit could be tuned to create a vanishingly small DC offset at the output of a split-rail stage following a single-rail stage or part without the use of an AC coupling capacitor and the attendant issues (distortion, bias, microphonic behavior, etc.)