<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>FPGA and DSP ep. 2: Implementing a folded FIR filter on FPGA</title><link>/members-area/personalblogs/b/blog/posts/fpga-and-dsp-ep-2-implementing-a-folded-fir-filter-on-fpga</link><description>This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can check it out here: https://youtu.be/LD8176BYne8</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>