<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>FPGA and DSP ep. 1:Efficient parallel FIR filter implementation on FPGA</title><link>/members-area/personalblogs/b/blog/posts/fpga-and-dsp-ep-1-efficient-parallel-fir-filter-implementation-on-fpga</link><description>Hello there, I made a video about FIR filter design on (Xilinx) FPGAs.You can check it out here: https://youtu.be/_1LlX-V5yCA Cheers!</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>