/members-area/personalblogs/b/blog/posts/fpgas-are-a-blastAbout a week ago I bought myself a USB Programmer for Altera FPGAs and CPLDs. The place I bought it from also had a small, simple CPLD board based on a Max II part for sale, so I got one of those too. The pair came to around &#163;16 and arrived the next en-USTelligent Community 12https://community.element14.com/members-area/personalblogs/b/blog/posts/fpgas-are-a-blastSat, 12 Jun 2021 20:44:29 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e1878a96-7131-449c-b636-41c0e4b2dba9Jan Cumps1<p>John, why do you put the assignment of io_1 to 4 in a process?</p><p>I&#39;ve seen the <a class="jive-link-external-small" href="https://www.gaisler.com/doc/vhdl2proc.pdf" rel="nofollow ugc noopener" target="_blank">two-process design method method</a> before. Is that the pattern you are using?</p><img src="https://community.element14.com/aggbug?PostID=11471&AppID=293&AppType=Weblog&ContentType=0" width="1" height="1">