Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA

RE: Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA

Jan Cumps — Fri, 02 Oct 2020 10:57:54 GMT

The original sources for this project aren't available anymore on the internet.

I attached my version to this post now. It's Magnus' project, but with input pulldowns disabled in the constraint file.

RE: Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA

shabaz — Fri, 20 Mar 2015 16:18:57 GMT

Hi Jan,

Great post!!! I've not tried to make the Papilio board into an OBLS since I have an OBLS board, but it is good to know there

is little difference apart from the level translator that needs adding.

It is extremely useful. I used it to decode a camera parallel bus - worked great!!

RE: Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA

johnbeetem — Thu, 19 Mar 2015 23:39:16 GMT

This is a nice 'blog. Thank you for posting it. I really like the Papilio boards.

This would be good material for element14's FPGA Group That group doesn't get a lot of traffic these days, which puzzles me: I don't know of a better site for general FPGA discussion and 'blogging. It's probably a chicken-and-egg problem and we just need people to post a lot more content there.