Rotary Encoders - Part 5: Capturing Input on an FPGA

RE: Rotary Encoders - Part 5: Capturing Input on an FPGA

Jan Cumps — Sat, 05 Jun 2021 16:40:03 GMT

I'm training Pynq and Zynq design.

I've tried to port the PWM module of this post to that architecture.

Instead of taking the input for PWM duty cycle from a rotary encoder, I take it from the embedded ARM controller.

Success:

[View:/resized-image/__size/620x604/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-5be56f7a-b794-4c61-8fea-fb0ae504f84c/8358.contentimage_5F00_203902.png:620:604]

I still have a lot to learn, but I managed to change the duty cycle from 6.5 to 15.5%, just like with the rotary encoder in the original post above

[View:/resized-image/__size/620x387/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-5be56f7a-b794-4c61-8fea-fb0ae504f84c/6215.contentimage_5F00_203903.png:620:387]

[View:/resized-image/__size/620x378/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-5be56f7a-b794-4c61-8fea-fb0ae504f84c/5710.contentimage_5F00_203904.png:620:378]

RE: Rotary Encoders - Part 5: Capturing Input on an FPGA

Jan Cumps — Fri, 17 Jul 2015 15:19:15 GMT

I finally managed to get that video uploaded.

[View:https://www.youtube.com/watch?v=gm-mlS4_pCQ:740:466]

RE: Rotary Encoders - Part 5: Capturing Input on an FPGA

michaelkellett — Wed, 15 Jul 2015 13:15:19 GMT

It's nice of you to invite me to comment - I'm kind of busy right now so I'll be brief.

First let me say that I appreciate the public service you do in posting this stuff so the last thing I want to do is nitpick about style.

There are two things that stand out:

1) You don't reset in your code - the world is divided on this but I find it is often very useful to have a way of resetting the FPGA.

2) You don't indent your if statements (may be an E14 problem)

I use a top level block diagram (and possibly lower level diagrams too) to instantiate and wire up entities (in AldecHDL). I find this makes complex designs much more understandable.

If your concern re PulseCount is this line:

if PulseCount < ("0001" & Position) then

then I don't see any problem except that a comment might help others to understand it, and of course it imposes some restrictions on the timing of your waveforms which may well be an acceptable tradeoff for simplicity.

Do you simulate your FPGA code before running it ?