RE: Verilog PWM

shabaz — Fri, 06 Oct 2017 15:23:25 GMT

fpga4fun and KNJN are about the worst websites for learning unfortunately. Their examples all use knjn.com boards (probably a related website) which ship with no schematics, and deliberate information hiding. Plus, some of their example projects do not come with source. They are a commercial enterprise with little interest in education it seems. Definitely worth avoiding : (

RE: Verilog PWM

michaelkellett — Fri, 06 Oct 2017 13:30:16 GMT

The original code is truly awful !

You don't mention any kind of reset - it is almost always a good thing to have a way of starting off in a known condition - hardware powers up as it likes - in FPGAs or ASICs you often need to set them up - so if this were my code there would be away of making sure that the counters start at zero and the outputs start at off.

Here's a style comment - and why everyone should learn VHDL:

ClkTick <= (ClkCount == ClkDiv - 2);

This may be legal in Verilog but it shouldn't be !

ClkTick is declared as reg so I assume you mean it to be some kind of hardware signal.

But you are assigning the result of a logical comparison to it - why not describe what you really want:

if (ClkCount == (ClkDiv - 2))

ClkTick <= 0;

else

ClkTick <= 1;

This is a simple example and it is clear to me what you mean, and probably clear to the compiler or Synthesizer.

When you get on to more complicated stuff it will bite you !

(The great thing about VHDL is that it never assumes anything - it is very strictly typed.)

(You'll notice that I don't assume precedence of - over ==

Since I work in C, VHDL, Verilog (a little) and a few other things too, I find the cost of brackets to be worth paying. [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-7e2be419-e1fc-4e1f-8d69-cca995fb620d/contentimage_5F00_1.png:16:16])

Hope this is helpful and thanks for your post.