RE: MOS 6526 CIA as a FPGA

genebren — Wed, 11 Jul 2018 21:26:47 GMT

Great project. I had to do a similar thing many years ago when a product that our company built relied on an old IEEE controller chip from Intel. We ran out of good choices to procure these chips so we decided to build one from a FPGA. We had no end of trouble in doing this, as the specifications for the controller did a very poor job of defining all of the signal timing. In the end, we bailed and bought chips on the gray market (fairly good yield). But, having said that, if you understand all of the timing and logic, it can be done.

I have designed glue logic out of CPLD (smaller than most FPGAs) using VDHL to define the logic. Here are some links to a few tutorials that I wrote on one of those projects. This should help you to understand how to write logic for some of those blocks in your diagram:

https://www.element14.com/community/external-link.jspa?url=https%3A%2F%2Fwww.embeddedrelated.com%2Fshowarticle%2F85.php - VHDL tutorial - A practical example - part 1 - Hardware

https://www.element14.com/community/external-link.jspa?url=https%3A%2F%2Fwww.embeddedrelated.com%2Fshowarticle%2F87.php - VHDL tutorial - A practical example - part 2 - VHDL coding

https://www.element14.com/community/external-link.jspa?url=https%3A%2F%2Fwww.embeddedrelated.com%2Fshowarticle%2F89.php - VHDL tutorial - A practical example - part 3 - VHDL testbench

As to some of your other questions on understanding your block diagram, I suggest that you write detailed questions, so people really understand what you are looking for.

Good luck. We are here to help.

Gene