High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

RE: High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

Robert Peter Oakes — Mon, 19 Nov 2018 15:12:30 GMT

I can see many uses for it no matter what it is called

4 DAC'S / ADC's in parallel for simultaneous update

Increased Memory utilizing 4 chips

pretty much any traditional SPI device utilizing the one wire in and one out * 4

Very handy

RE: High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

Robert Peter Oakes — Sat, 17 Nov 2018 23:31:52 GMT

Once you start making the transfer parallel, is it really SPI any more (Serial Peripheral Interface), especially if you take it to 8 lines in parallel. At what point does it cease to be SPI.

Don't get me wrong, improving data transfer like this is awesome and is a common (or should be) way of speeding up transfer of data to a graphic display for instance were even the highest single data line spi would give poor refresh rates.

Great post, keep it coming [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-fcdc9280-4d59-4a83-b94e-afb4b3bb7292/contentimage_5F00_1.png:16:16]

RE: High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

Jan Cumps — Sat, 17 Nov 2018 21:05:48 GMT

The blog post is finally finished. I've added captures from the logic analyser.

RE: High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

DAB — Sat, 17 Nov 2018 19:36:12 GMT

It is an interesting way to use four serial ports to do pseudo-parallel data transfer.

I wonder how it would stack up to just using five digital I/O pins to act as a parallel port transfer.

DAB

RE: High Throughput SPI traffic part 4a - SPI Master with DMA and Parallel Data Lines

Jan Cumps — Fri, 16 Nov 2018 18:07:26 GMT

this blog is not finished. Not even 50%. I accidently published it.