RE: Getting up and running with Arm Design Start, Generating the SW

jlbrian — Sun, 17 Mar 2019 15:55:43 GMT

I followed the first tutorial, and that seems to be working. I got the following in the putty terminal:

[View:/resized-image/__size/620x405/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-e2de024b-d4a0-44ee-a0a0-01715771a12a/3187.contentimage_5F00_189531.jpg:620:405]

and all of the buttons and switches seem to be responding appropriately, however, when I go to export hardware I get the following dialog:

[View:/resized-image/__size/534x182/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-e2de024b-d4a0-44ee-a0a0-01715771a12a/6215.contentimage_5F00_189532.jpg:534:182]

Did I miss a step?

This is the console output:

start_gui

open_project C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.xpr

INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

Current project path is 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7'

open_project C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.xpr

Current project path is 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7'

INFO: [Project 1-313] Project file moved from 'V:/hardware/m3_for_arty_a7/m3_for_arty_a7' since last save.

CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/Micron_N25Q128A13E/code/N25Qxxx.v', nor could it be found using path 'V:/hardware/m3_for_arty_a7/testbench/Micron_N25Q128A13E/code/N25Qxxx.v'.

CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/S25fl128s/model/s25fl128s.v', nor could it be found using path 'V:/hardware/m3_for_arty_a7/testbench/S25fl128s/model/s25fl128s.v'.

CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/sfdp.vmf', nor could it be found using path 'V:/hardware/m3_for_arty_a7/testbench/sfdp.vmf'.

Scanning sources...

Finished scanning sources

WARNING: [Project 1-509] GeneratedRun file for 'synth_1' not found

WARNING: [Project 1-509] GeneratedRun file for 'impl_1' not found

WARNING: [filemgmt 56-2] IPUserFilesDir: Could not find the directory 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.ip_user_files', nor could it be found using path 'V:/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.ip_user_files'.

CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:arty:part0:1.1. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/vivado/Arm_ipi_repository'.

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.

open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 800.305 ; gain = 105.840

update_compile_order -fileset sources_1

close_project

open_hw

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1704] No user IP repositories specified

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.

open_hw: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 851.555 ; gain = 0.000

open_project C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.xpr

Current project path is 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7'

CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/Micron_N25Q128A13E/code/N25Qxxx.v'.

CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/S25fl128s/model/s25fl128s.v'.

CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/testbench/sfdp.vmf'.

Scanning sources...

Finished scanning sources

WARNING: [filemgmt 56-3] IPUserFilesDir: Could not find the directory 'C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7.ip_user_files'.

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/vivado/Arm_ipi_repository'.

INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.

open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 859.746 ; gain = 8.191

current_project {New Project}

close_project

****** Webtalk v2018.2.2 (64-bit)

**** SW Build 2348494 on Mon Oct 1 18:25:44 MDT 2018

**** IP Build 2318053 on Mon Oct 1 21:44:26 MDT 2018

source C:/Users/Jeramy/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-17340-DESKTOP-90VHBE3/webtalk/labtool_webtalk.tcl -notrace

INFO: [Common 17-206] Exiting Webtalk at Sun Mar 17 08:59:15 2019...

update_compile_order -fileset sources_1

open_bd_design {C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/block_diagram/m3_for_arty_a7.bd}

Adding cell -- xilinx.com:ip:axi_bram_ctrl:4.0 - axi_bram_ctrl_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_bram_ctrl_0_0

INFO: [xilinx.com:ip:axi_bram_ctrl:4.0-2] m3_for_arty_a7_axi_bram_ctrl_0_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.

INFO: [xilinx.com:ip:axi_bram_ctrl:4.0-1] m3_for_arty_a7_axi_bram_ctrl_0_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.

Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_gpio_0_0

ERROR: [IP_Flow 19-3461] Value 'dip_switches_4bits' is out of the range for parameter 'GPIO2 BOARD INTERFACE(GPIO2_BOARD_INTERFACE)' for BD Cell 'axi_gpio_0' . Valid values are - Custom

ERROR: [IP_Flow 19-3461] Value 'led_4bits' is out of the range for parameter 'GPIO BOARD INTERFACE(GPIO_BOARD_INTERFACE)' for BD Cell 'axi_gpio_0' . Valid values are - Custom

Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_gpio_1_0

ERROR: [IP_Flow 19-3461] Value 'rgb_led' is out of the range for parameter 'GPIO BOARD INTERFACE(GPIO_BOARD_INTERFACE)' for BD Cell 'axi_gpio_1' . Valid values are - Custom

ERROR: [IP_Flow 19-3461] Value 'push_buttons_4bits' is out of the range for parameter 'GPIO2 BOARD INTERFACE(GPIO2_BOARD_INTERFACE)' for BD Cell 'axi_gpio_1' . Valid values are - Custom

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_interconnect_0_0

Adding cell -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_quad_spi_0_0

ERROR: [IP_Flow 19-3461] Value 'qspi_flash' is out of the range for parameter 'QSPI Board Interface(QSPI_BOARD_INTERFACE)' for BD Cell 'axi_quad_spi_0' . Valid values are - Custom

INFO: [IP_Flow 19-3438] Customization errors found on 'axi_quad_spi_0'. Restoring to previous valid configuration.

ERROR: [IP_Flow 19-3439] Failed to restore IP 'axi_quad_spi_0' customization to its previous valid configuration.

ERROR: [BD 41-245] set_property error - Value 'qspi_flash' is out of the range for parameter 'QSPI Board Interface(QSPI_BOARD_INTERFACE)' for BD Cell 'axi_quad_spi_0' . Valid values are - Custom

Customization errors found on 'axi_quad_spi_0'. Restoring to previous valid configuration.

Failed to restore IP 'axi_quad_spi_0' customization to its previous valid configuration.

ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

ERROR: [BD 41-1273] Error running init TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

::xilinx.com_ip_axi_quad_spi_3.2::init Line 8

Adding cell -- xilinx.com:ip:axi_uartlite:2.0 - axi_uartlite_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_uartlite_0_0

Adding cell -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_blk_mem_gen_0_0

INFO: [Device 21-403] Loading part xc7a35ticsg324-1L

Adding cell -- xilinx.com:module_ref:tri_io_buf:1.0 - tri_io_buf_0

INFO: [IP_Flow 19-234] Refreshing IP repositories

INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/vivado/Arm_ipi_repository'.

INFO: [BD 41-1728] Could not find a module with name: m3_for_arty_a7_tri_io_buf_0_0

Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xlconcat_0_0

Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xlconcat_1_0

Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xlconstant_1_0

Adding cell -- Arm.com:CortexM:CORTEXM3_AXI:1.0 - Cortex_M3_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_Cortex_M3_0_0

cell handle is /Cortex_M3_0

CRITICAL WARNING: [BD 41-5] axi_gpio_0 does not have a bus interface called GPIO2

CRITICAL WARNING: [BD 41-5] axi_gpio_1 does not have a bus interface called GPIO2

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_interconnect_0_1

Adding cell -- xilinx.com:ip:axi_quad_spi:3.2 - axi_single_spi_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_single_spi_0_0

Adding cell -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_quad_spi_0_1

Adding cell -- xilinx.com:ip:axi_quad_spi:3.2 - axi_xip_quad_spi_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_xip_quad_spi_0_0

Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_gpio_0_1

Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - axi_protocol_convert_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_axi_protocol_convert_0_0

Adding cell -- Arm.com:user:DAPLink_to_Arty_shield:1.0 - DAPLink_to_Arty_shield_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_DAPLink_to_Arty_shield_0_0

Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xbar_0

Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xbar_1

Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_auto_pc_0

Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_DAPLink

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_proc_sys_reset_DAPLink_0

Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_base

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_proc_sys_reset_base_0

ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'proc_sys_reset_base' . Valid values are - Custom

Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - i_interconnect_aresetn

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_i_interconnect_aresetn_0

Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - i_peripheral_aresetn1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_i_peripheral_aresetn1_0

Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - i_sysresetn_or

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_i_sysresetn_or_0

Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - i_inv_dbgresetn

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_i_inv_dbgresetn_0

Adding cell -- xilinx.com:ip:util_vector_logic:2.0 - i_inv_sysresetn1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_i_inv_sysresetn1_0

Adding cell -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_clk_wiz_0_0

Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_1

INFO: [BD 41-434] Could not find an IP with XCI file by name: m3_for_arty_a7_xlconstant_1_1

Successfully read diagram <m3_for_arty_a7> from BD file <C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/block_diagram/m3_for_arty_a7.bd>

INFO: [BD 41-433]

Design successfully migrated to use XCI files...

Wrote : <C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/block_diagram/ui/bd_a2e86b50.ui>

open_bd_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:51 . Memory (MB): peak = 1200.547 ; gain = 331.961

ERROR: [Common 17-39] 'open_bd_design' failed due to earlier errors.

update_compile_order -fileset sources_1

open_hw

connect_hw_server

INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121

INFO: [Labtools 27-2222] Launching hw_server...

INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2018.2.2

**** Build date : Oct 1 2018-20:15:45

connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1218.250 ; gain = 0.000

open_hw_target

INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319A7667FA

open_hw_target: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1876.188 ; gain = 657.938

current_hw_device [get_hw_devices xc7a35t_0]

refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]

INFO: [Labtools 27-1435] Device xc7a35t (JTAG device index = 0) is not programmed (DONE status = 0).

set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]

set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]

set_property PROGRAM.FILE {C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/m3_for_arty_a7/m3_for_arty_a7_reference.bit} [get_hw_devices xc7a35t_0]

program_hw_devices [get_hw_devices xc7a35t_0]

INFO: [Labtools 27-3164] End of startup status: HIGH

refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]

INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.

WARNING: [Labtools 27-3361] The debug hub core was not detected.

Resolution:

1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.

2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.

For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

open_bd_design {C:/Users/Jeramy/Documents/XILINX/AT426-BU-98000-r0p0-00rel0/hardware/m3_for_arty_a7/block_diagram/m3_for_arty_a7.bd}