YAPS Part Twelve - Design revisited: reworking the layout and PCB

RE: YAPS Part Twelve - Design revisited: reworking the layout and PCB

Andrew J — Thu, 05 Sep 2019 13:07:19 GMT

A quick update on this. I received the boards and populated but I don't think I did a great job of soldering - which is a shame as I'd done alright up to now. Anyway, turning on, I could only get 19V out (rather than the max 15V) and no amount of twiddling with the Voltage/Current Pots did anything; one of the Linear Regulators got to 80C quite quickly whilst the other didn't rise in temperature at all. Current pot had zero impact; the voltage pot turned output voltage down to 10V when it was fully wound to 0Ohms. The load switch also dropped the voltage to 10V (which was in line with the 0Ohm Voltage pot) so somewhere along the line something was wrong and slinging out a minimum 10V. I found a dodgy connection on the output of the second Linear Regulator and also found that the Mosfet was completely open - connectivity between drain and source and gate.

I resoldered the Linear Regulator and that seems ok now - at least, I can see continuity from the output leg and the tab which was erratic before. I also removed and replaced the Mosfet. I did check for overshoot on Vin first: set the trigger to 29V on a rising edge and turned on, but there was no triggering.

At the moment I am getting around 20mV on the Switching Node. Gate is swinging up to around 5V but the Switching pin seems to be doing nothing. I suspect that the DC-DC converter has blown: might not be surprising if the Mosfet was open and 26V was flowing through the gate, switch and feedback pins. It could be the Schottky Diode. Of course, there could now be issues with the Linear Regulators, the Current Source and other components.

So the upshot is, I'm deciding whether its worth restocking the parts yet again. Some of these I only seem to be able to source from the US and all told, it would be another £40 or so. I may be as likely to damage them soldering as not which is a concern (I'm assuming the Mosfet wasn't faulty until I soldered it to the board but I suppose it may have been) I could assume the parts on the first version board are ok and remove them - I'd need to invest in a hot air rework station for that. If I could work out what was actually wrong so I had a little more confidence on what to change I'd be happier.

RE: YAPS Part Twelve - Design revisited: reworking the layout and PCB

Andrew J — Sat, 17 Aug 2019 17:10:10 GMT

This is it, I'm committing to this layout of the Switching circuit, otherwise I'll tweak it forever.

[View:/resized-image/__size/620x622/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-893e6571-d02f-48c5-bcd1-0dbf09a9e430/5700.contentimage_5F00_204966.png:620:622]

I've pulled components in but kept some distance between the Cin1 an Cout1 - although the only reference to this distance came from Micro Rohm and I could find no other mentions. Feedback traces are away from the noisy nodes. The parts have an orientation and a distance that will allow for hand-soldering. Hence the thermal reliefs (I'm still looking at the pros/cons of hand-soldering without these.) Board real estate also looks optimal.

Here's a version with loops and SW node highlighted:

[View:/resized-image/__size/620x703/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-893e6571-d02f-48c5-bcd1-0dbf09a9e430/2656.contentimage_5F00_204967.png:620:703]

In all the permutations of layout, this looks like the best trade off. SW node is small. The right hand loop is 37mm long; left one a few mm shorter. My first attempt probably had a shorter right hand loop equivalent but a longer left hand loop: looking at the grid in that image at 5mm steps there's little in it. The only thing I can do to tighten it further is to remove R2, R3, R5 and C5 which are there as placeholders if needed to help deal with ringing and noise. R2 and R3 will be populated with a 0 ohm resistor (<5mOhm). R5 and C5 will be left unpopulated until, and if, needed.

I can't get any more thermal relief for the MOSFET but all my calculations, and re-calculations, show this won't be an issue - my last set showed it getting to 37C from a 25C ambient and empirical evidence from soak testing is showing 46-47C after an hour.

Not shown is the GNDPWR plane on layer 2 which extends across the board - the vias that seem to go nowhere, go there. Switcher GND, ITH/Run, FB pins connect to GNDPWR at NT1 which is where SIGNAL GND will connect (layer 3.)

Thanks again for all the input.

RE: YAPS Part Twelve - Design revisited: reworking the layout and PCB

jc2048 — Wed, 14 Aug 2019 10:40:55 GMT

So 'Z' grounds are good after all?

I don't know if this will help the discussion, but I've drawn the switching currents for the regulator circuit on your layout in orange.

[View:/resized-image/__size/620x588/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-893e6571-d02f-48c5-bcd1-0dbf09a9e430/8422.contentimage_5F00_204960.png:620:588]

This is my understanding of what's going on, but I'll just say I wasn't taught this stuff formally so don't rely on what I'm saying and feel free to question it. Like many engineers, I ended up having to deal with switching circuits but haven't gone much beyond using them as POL on digital boards and as LED drivers [in both situations you tend to follow recommended layouts and do a bit of extra filtering to get past EMC, and neither is as challenging as the more analogue-like thing you're trying for

here]. This will sound like a lecture but believe me it isn't.

The small 'dashed' arrows indicate where the switching currents switch on and off. The continuous stretches are where the current ramps up and down giving current ripple (assuming it's working in continuous mode). There are two loops corresponding to whether the MOSFET is on or off - remembering that the Schottky is also a switch (albeit not controlled directly by the controller) - a large loop and a small one. To keep the noise down, you need to minimise the inductance which you can do by minimising the area of the loop. You particularly need to try and minimize the inductance in the large loop you have here. You need to minimize the inductance because it's going to generate a voltage spike when the current abruptly stops [the parasitic inductance will get rid of its stored energy by generating an emf and coupling the energy elsewhere].

The other major noise generator is the switching node which I've outlined in yellow. The voltage waveform there has an amplitude of the full supply voltage and is driven with a high current so the edges will readily capacitatively couple to anything it can develop a voltage field with. In your case that's mostly the 'shield' layer. I'm very unsure of the next bit, but I think that might result in charge mainly moving across the shield from/to the tie point [yellow line], so potentially there might be coupling back up in the area you've marked as feedback. I'm unsure because I can't really quantify it. The plane is metal and a low impedance but it takes time for the change to propagate across. The edge rate will be crucial to all this and given the reverse capacitance of the Schottky it probably can't move fast enough to give the kind of problem I'm envisioning. And now we have a current on the go - remember currents flow in loops - we need to think what is driving it and where does the return go on the top surface.

The return presumably either flows through the power ground, 'through' the output capacitors, to the other end of the coil when it's that that's driving the change or to the input capacitors when the MOSFET is driving the change. You can see how convoluted this stuff gets and how you tie yourself in knots with it. Anyway, what you've done with the shield may be brilliant or it may be awful (but I'm not sure the input is the place to tie it).

To be more practical, rather than analyse this to death, I'd suggest you might try alternative layouts on a piece of paper. You could probably manage something where the grounds of the input and output capacitors were much closer together and not at the extremes of a 'Z'.

RE: YAPS Part Twelve - Design revisited: reworking the layout and PCB

genebren — Sun, 11 Aug 2019 23:11:02 GMT

Andrew,

First off, I appreciate that you gave my comments/suggestions consideration, even if you decided to go a different way. I do understand the reasons behind your choices.

Look over the gerbers, I do see a great improvement both in placement and routing. Here are a couple of comment/suggestions:

It seems to me that the GND (-Ve) get a little thin under U1. This might be another place to use vias to another layer to improve current flow.
Polygons around R4 (+Ve) could be a little more generous (3 of 4 thermal connects). Also a little more space between R4 and Q1 might improve current carrying ability (the polygon gets pretty thin between the two components).
Polygon containing L1 pin 1 and Q2 is a little like the above note. A little space between Q1 and L1 might help.
The polygon connecting pin2 of L1 could be enlarged around pin2 to all 4 thermal connects (currently only 2 exist).
The polygon bridging R13 (pin1) and U3 and U4 could use some enlarging around the high current connection of R13, U3 and U4). I would also look to see if there might be a routing of U3 to R18 and U4 to R19 where you might be able to get a slightly thick trace (like moving C20 to the left and running the trace initially to the right and then up to R19). You might be able to do the same with U3/C30.
I am not really sure what is happening with U6 (possible hall effect current sensor?), put the resolution of the image makes all the pins of U6 to look shorted. I did not check the gerbers directly as I don't have a good view option.

I really like the annotations that you place on the top layer. In general the high power currents seem to be well routed and high and low current paths seem to be separated, keeping current out of the shielding. Well done! I do like how you connected the shields at a single point. It is a little troubling that the -Ve flow is long and broken between layers, with several via bridges, but sometimes you just have to do what you can.

Good luck as you continue to move forward.

Thank you for bringing an interesting series of blogs to the forum and allowing everyone to follow along on an interesting and challenging design!

Gene

RE: YAPS Part Twelve - Design revisited: reworking the layout and PCB

three-phase — Sun, 11 Aug 2019 20:38:59 GMT

Good to see the progress you are making and the solutions to the problems you are trying to tackle. They are all beyond my technical knowledge, but good luck with the next build.

Kind regards.