Efinix Dev Board - setting up IO and PLL/members-area/personalblogs/b/michael-kellett-s-blog/posts/efinix-dev-board---settiong-up-io-and-pllIn the first blog of this series there is a schematic which shows the two AP Memory APS6404L Pseudo SRAMs connected to the FPGA. These can be clocked at a maximum rate of 130MHz, but there are some issues in going that fast &ndash; firstly the maximu...en-USTelligent Community 12RE: Efinix Dev Board - setting up IO and PLLhttps://community.element14.com/members-area/personalblogs/b/michael-kellett-s-blog/posts/efinix-dev-board---settiong-up-io-and-pllMon, 02 Jan 2023 19:37:18 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b48fb27a-3163-44f5-9070-2ac1dc4aef78DAB0<p>Nice post.</p> <p>I enjoyed this type of work in my younger days, but it is now beyond me.</p> <p>Well done.</p><img src="https://community.element14.com/aggbug?PostID=25001&AppID=323&AppType=Weblog&ContentType=0" width="1" height="1">RE: Efinix Dev Board - setting up IO and PLLhttps://community.element14.com/members-area/personalblogs/b/michael-kellett-s-blog/posts/efinix-dev-board---settiong-up-io-and-pllSat, 31 Dec 2022 17:30:04 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b48fb27a-3163-44f5-9070-2ac1dc4aef78dougw0<p>I am enjoying your walk-through of bringing this card up, especially the commentary on strategies employed by different tools. Thanks.&nbsp;</p><img src="https://community.element14.com/aggbug?PostID=25001&AppID=323&AppType=Weblog&ContentType=0" width="1" height="1">RE: Efinix Dev Board - setting up IO and PLLhttps://community.element14.com/members-area/personalblogs/b/michael-kellett-s-blog/posts/efinix-dev-board---settiong-up-io-and-pllSat, 31 Dec 2022 15:32:55 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b48fb27a-3163-44f5-9070-2ac1dc4aef78scottiebabe0<p>You make using FPGAs look so easy! Nice work [emoticon:c4563cd7d5574777a71c318021cbbcc8]</p><img src="https://community.element14.com/aggbug?PostID=25001&AppID=323&AppType=Weblog&ContentType=0" width="1" height="1">