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AUBoard 15P AUBoard-15P onboard JTAG adapter stability issue
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  • AUBoard-15P
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AUBoard-15P onboard JTAG adapter stability issue

MkE
MkE over 1 year ago

Hello,

On a newly purchased AUBoard-15P wirth original reference design loaded with no changes, we have stability issue with JTAG connection while using the onboard FTDI. The board is discovered in Vivado HW Manager initially, but after few minutes, the JTAG connection starts cycling on and off with pop-up in Vivado with "No HW target open" that promptly dissapears - with about 1-2s interval.

Sysmon data is getting corrupted with zero values being inserted in the plots. After some time Vivado crashes due to this problem.

The setup was tested with four different USB cables, three desktops, Vivado 2023.2 and 2024.2 both on Linux and Windows. FTDI drivers are updated to latest version.

Measured internal temperature of FPGA never goes above 45°C. Adding extra heatsink to FPGA had no effect past lowering the mesured temperature below 40°C.

Reading the devboard ERRATA, there is mention about JTAG functionality being impaired above 55°C - this sounds like some aspect of the design is marginal and some production units manifest the same problem even at lower temperatures.

Can you please elaborate on the errata and expected behaviour?

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  • MkE
    MkE over 1 year ago in reply to iksevas +1
    Same mail as this profile, I posted here only after not getting any response. I also asked for full schematic of the devboard with same outcome. I would fully expect the inventory being delivered reworked…
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  • iksevas
    iksevas over 1 year ago

    image

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  • iksevas
    iksevas over 1 year ago in reply to iksevas

    U23 translator even though rated for the solution doesn’t behave well as temperatures increase.

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  • MkE
    MkE over 1 year ago in reply to iksevas

    Thank you for confirming the problem being by design.

    I would suggest updating the errata to stating that the JTAG is not functional above 30°C, because that is the result we are getting with our board.

    What is the recommended path forward - should we RMA the board, or perform rework on brand new devkit to get it operational?

    Bott side E0,95top side thermal E0,95

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  • michaelkellett
    michaelkellett over 1 year ago in reply to iksevas

    Interesting - from your schematic the NVT2006  appears to be translating between 0.84V and 3.3V logic levels. The chip is now obsolete but was rated by NXP as being suitable for operation at no lower than 1.0V on the A port.

    I didn't look hard but I couldn't find a 6 bit level shifter that can do 0.8V to 3.3V !

    Rather makes you wonder why on earth AMD/Xilinx didn't put a level translator inf the FPGA on the JTAG port, and even more why Avnet didn't put the effort into a work around on the board.

    MK

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  • iksevas
    iksevas over 1 year ago in reply to michaelkellett

    That is VCCO for bank 0 and bank 84. Translator is performing 1.8V to 3.3V translation.

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  • michaelkellett
    michaelkellett over 1 year ago in reply to iksevas

    Woops !

    Sorry.

    MK

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  • wwilly
    wwilly over 1 year ago in reply to iksevas

    Would passing via a Platform Cable USB on J10 instead of the USB-to-JTAG interface J9+U21 would face the same issue?

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  • iksevas
    iksevas over 1 year ago in reply to wwilly

    Yes - the JTAG lines are shared on J10 / J9 and they feed the same problematic translators.

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  • iksevas
    iksevas over 1 year ago in reply to wwilly

    Yes - the JTAG lines are shared on J10 / J9 and they feed the same problematic translators.

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