AUBoard 15P - Recent Threads

OOB - QC test not passed

iulyanov — Wed, 11 Mar 2026 16:44:26 GMT

Hello,

I am working with the AUBoard-15P carrier together with my own custom FMC card. Earlier, my FMC card had a hardware issue that caused voltage drops on the AUBoard 3.3 V rail. I have now removed the FMC card and I am trying to restore the board to a known-good state by reflashing the official Out-of-Box image to the on-board QSPI flash.

I used the OOB package from: http://avnet.me/auboard-15p-dk-oob and programmed the provided au15p_firmware.mcs into QSPI using Vivado Hardware Manager.

After reflashing, the board no longer starts the web-server demo.
Instead, the UART log shows:

AU15P Board SPI Flash Bootloader v1.0 Build on Oct 15 2024
INFO: QC test not passed, launch QC test program now.
Boot application AU15P_TEST.elf
..
XEMacLite detect_phy: PHY detected at address 1.
auto-negotiated link speed: 100

The bootloader launches AU15P_TEST.elf instead of the expected OOB application / web server.

So, my question is

Is the QC/test application source code available, or at least a description of what it checks? I would like to identify whether the earlier FMC-related fault may have damaged some part of the carrier board. I have strong concerns about it.
Maybe I am using an OOB image that is not appropriate for my board version, and the board itself is OK? My board is AUB-15P-DK-PCB-1

Any guidance would be appreciated. Thank you.

When will rev 2 be available?

dmeads_70 — Thu, 12 Feb 2026 04:34:49 GMT

I am considering this board and have been browsing this forum looking at issues and solutions.

I read about the JTAG level translator and how it does not work properly above 30 *C. I understand this is being worked on for revision 2 of the board.

Wondering when revision 2 will be available?

Thank you!

Controlling AUBoard-15P form Matlab using the JTAG to AXI interface

Umallik — Mon, 02 Feb 2026 16:08:38 GMT

My project requires control of an AUBoard-15 from Matlab (using the Matlab generated JTAG to AXI block). To that end I am required to create a Board definition file using the interface provided in Matlab. Can someone help me with the entries requested below. I do not have access to the schematics. I am not sure how to go about coming up with answers to these questions.

How to enable the PG_C2M (power good to mezzanine) signal on the AUBOARD 15P?

alainsan — Fri, 21 Nov 2025 00:56:54 GMT

My assembly is the AUBOARD 15P + Analog Devices AD-FMCOMMS4 RF board plugged in via the FMC connector.
An essential signal on the AUBOARD 15P is the PG_C2M (power good to mezzanine) to enable the power on the RF board.
I could not find any documentation as to how to enable this signal (any jumper, resistor/??)

More generally, the AUBOARD 15P schematics would be extremely helpful.

The D29 LED is off (meaning PG_C2M is 0).

Any help will be greatly appreciated

the auboard_hdmi_pass_thru example design missing directions?

rowanham — Fri, 10 Oct 2025 00:51:53 GMT

I have an aub15p board. I am trying to build the auboard_hdmi_pass_thru example design, but there are no instructions on how to do this. The three pages of documentation don't mention any changes to update the project from the 2023 software to the 2025 software. Is there a document I am missing?

AUBoard 15P Vivado Board file issues

gianluca.garoia — Fri, 29 Aug 2025 13:33:41 GMT

Hi,

as from subj, working with AUBoard15P with Vivado 2025.1, seeing the following issues:

1) in IP Integrator Board tab the AUBoard peripherals + reset are present, but the 300 MHz system clock is missing, and trials to insert it form the Vivado Automation (from "Connection Automation" or from the GUI of Clocking Wizard) also fails, these last two case gives the error:

ERROR: [Common 17-69] Command failed: Failed to get scope property. Unknown property 'VLNV'

Manually deifning this clock and manually constraining it in xdc of course owrks, but the question is about the board files and the automation not working: is this a bug of the board file or not? Any workaround about it?

2) By updating the Vivado Board Catalog from the Refresh button, the AUBoard is not present - at least for my installation, where for example the Avnet ZUBoard is correctly present - solution was to manually install the boar file under ~/.Xilinx/Vivado/2025.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2025.1/boards/Avnet

But any clue or better workaround why the Refresh button does not add the AUBoard?

Thaks in advance

AUBoard 15P Schematics/FAE contact

sray — Fri, 22 Aug 2025 18:17:44 GMT

AUBoard 15P Schematics

Hello,

I am interested in getting access to the schematics for the AUBoard 15P development board. I am at a stealth startup in Palo Alto, CA and we will be using this development board for FPGA bringup. Having access to these schematics will help guide us in the design-in of this FPGA into our product.

I understand I likely need to get in touch with an Avnet FAE to get access to the schematics. What is the best way to get in contact with the right person? Documentation suggests starting here.

Thanks,
Steve

Avnet AU board-15P(AES-AUB-15P-DK-G, Rev 01) - LVDS IO Standard

Mitilesh — Sat, 16 Aug 2025 08:19:57 GMT

I am mapping LVDS signals whiah are routed to bank 66/86 of FPGA. I am using LVDS IO standard of LVDS_18 as per the reference user_constarints.xdc file available in the following link
https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/auboard-15p-fpga-development-kit/

But vivado - v.2024.2 tool is indicating this as a critical warning mentioning unknown IO standard.

Should we ignore this warning or proceed with tool suggested IO standard?

Avnet AU board-15P(AES-AUB-15P-DK-G, Rev 01) - FMC connector issue

Mitilesh — Sat, 16 Aug 2025 08:10:56 GMT

I am interfacing Avnet AU board-15P(AES-AUB-15P-DK-G, Rev 01) with LVDS transmitter on it, to communicate with a external LVDS receiver through FMC connector. I observed that some pins of the FMC connector are mapped to HPIO capable signals and others are mapped to HDIO capable signals.

From the datasheet of Artix-Ultrascale+ FPGA, it is understood that HDIO signals maximum supported data rate is 250Mbps whereas HPIO capable pins support 2.5Gbps.

However, Assigning HDIO signals with lower data rate to FMC connector doesn't seem to be aligned with the FMC standard.

The basic requirement for our design is to have a interface that support LVDS transmission with data rate of at least 625Mbps.
I can see a warning in vivado- v 2024.2 tool mentioning illegal placement on those pins. Even though this is a warning, I could see signal integrity issue in the output.

Some of the HDIO signals that are mapped to FMC are following pairs:
(H14, G14)
(J14, J15)
(J12, H12)
(E13, E12)

Attaching the warnings for reference:

Is there any way to have work around for this issue?

AUBoard 15P PCIe interface is not working

dgfernandez — Mon, 28 Jul 2025 18:19:35 GMT

I am trying to connect the AU15 board to a PC via the PCIe interface. I have followed the tutorial in the documentation but I cannot get the root complex to enumerate the FPGA as an endpoint.

PCIe example:
www.hackster.io/.../perfecting-pcie-with-auboard-8cabd5

I have several doubts:

1. In the tutorial and in the board configuration files (previously exported to Vivado), the PCIe clock reference is listed as 100MHz, but the documentation (AUBoard-15P Development Kit Hardware User Guide Version 1.4) indicates that it is 125MHz.

2. On the other hand, the IP cores associated with the PCIe interface (XDMA, AXI-PCIe bridge) use a different pin assignment than the documentation (implying lane reversal).

3. It is indicated that the default lane size selection is 4-lane (J22 pins 2 and 3, shunted), but by default there is no jumper connected.

I have requested the schematics from our FAE. Once we have them, I assume we will be able to resolve these issues, but as this is urgent, I would like to know if anyone knows the answer to these questions.

Thank you. Best regards.

Setting up the AUBoard-15P in Vivado

Penguingineer — Fri, 20 Jun 2025 19:08:45 GMT

Hello,

The issue:

I recently purchased the AUBoard 15P FPGA Development Kit, and I want to set up my Vivado 2024 installation so that it can recognize this development kit. I downloaded the board definition files from the Avnet Github page (https://github.com/Avnet/bdf), but Vivado isn't listing the AUBoard 15P board as an option for new projects.

Fix attempt #1:

Vivado lists this location for board definition files for version 2021 and up, so I added it to my list of board repositories, but Vivado still isn't doesn't list the board as an option, so I can't select it when creating a new projecft:
<Vivado Install>\<Vivado_version>\data\xhub\boards\XilinxBoardStore\boards\Xilinx\

https://adaptivesupport.amd.com/s/article/The-board-file-location-with-the-latest-Vivado-tools

Fix attempt #2:

I found an article that creates an AUBoard project using Vivado by first creating a project from a VCU118 evaluation board, and then changes the target board to the AUBoard. I am unable to create a project using the VCU118 evaluation board, because after I download it, it disappears from the list of selectable boards:

www.hackster.io/.../4k-at-60hz-not-a-problem-with-the-auboard-b232b6

I need help to get Vivado to recognize the AUBoard, so I can create a new project. If anyone can provide any insight as to what might be going wrong here, I would be extremely grateful!

Thank you,

- Austin

A malfunction in the AUBoard 15P with the OOB Reference Design

ichead — Thu, 05 Jun 2025 17:39:40 GMT

Hello,

I would like to inquire about the abnormal behavior of my AUBoard. Suddenly my AUBoard is not working properly, even the OOB reference design is not working.

After power cycling the board, the SPI Flash OOB design should be written properly, and the blue DONE LED should light up. The terminal should display "AU15P Board SPI Flash Bootloader v1.0 Build on Oct 15 2024," but it didn't progress to the next message: "Boot application AU15P_OOB.elf."

With XSDB, MicroBlaze appears to be running, but when I use the stop/rst/con commands, I only see the "AU15P Board SPI Flash Bootloader v1.0 Build on Oct 15, 2024" message, and it doesn't progress any further.

When I press the RESET or PROG_B push switches, the same message appears, but nothing else happens, as shown in the attached file.

The OOB was working fine when I followed the Getting Started Guide, but it stopped working suddenly.

I suspect that MicroBlaze is not allowing the elf file to work properly.

Please let me know what I need to do or investigate to resolve this issue. Any advice on this would be appreciated.

Invalid AC Coupling values on PCIe

Aenerine — Tue, 13 May 2025 08:17:01 GMT

The board uses the default AC-coupling capacitor values on the PCIe edge connector.
This probably comes from the GTH transceiver user guide and doesnt take into account requirements comming from the PCIe standard.
As such, the board might have difficulties working at PCIe Gen 3.0 / 4.0.

AUBoard-15P onboard JTAG adapter stability issue

MkE — Fri, 04 Apr 2025 10:35:49 GMT

Hello,

On a newly purchased AUBoard-15P wirth original reference design loaded with no changes, we have stability issue with JTAG connection while using the onboard FTDI. The board is discovered in Vivado HW Manager initially, but after few minutes, the JTAG connection starts cycling on and off with pop-up in Vivado with "No HW target open" that promptly dissapears - with about 1-2s interval.

Sysmon data is getting corrupted with zero values being inserted in the plots. After some time Vivado crashes due to this problem.

The setup was tested with four different USB cables, three desktops, Vivado 2023.2 and 2024.2 both on Linux and Windows. FTDI drivers are updated to latest version.

Measured internal temperature of FPGA never goes above 45°C. Adding extra heatsink to FPGA had no effect past lowering the mesured temperature below 40°C.

Reading the devboard ERRATA, there is mention about JTAG functionality being impaired above 55°C - this sounds like some aspect of the design is marginal and some production units manifest the same problem even at lower temperatures.

Can you please elaborate on the errata and expected behaviour?

Unspecified / Undocumented PINs on AUBoard15P

Aenerine — Mon, 17 Feb 2025 14:29:28 GMT

Hello,
I was trying to figure out the functionality of the "HDMI_TX_EN" pin with location constraint set to FPGA PIN Y23.
There is no information in the documentation on how this pin is routed and what exactly it controls. Based on its name I can only guess its functionality.
Would love to see a more detailed description on the board's HDMI topology, used silicon chips and initial configuration of those components.

For example, there is no information on what is the default configuration of the U56 (How is the OTP configured?) or what TMDS redriver chips are used.
The "List of Features" in the hardware guide list only "HDMI TX and RX Interfaces" (Without anything else), which I consider quite insufficient for the purposes of the documentation.
Please add the missing information.
Thank you

Missing I2C Address of U56 (8T49N241) for AUBoard-15P

Aenerine — Thu, 13 Feb 2025 08:29:08 GMT

Hello,
The Hardware Guide 1.3 lists the I2C configuration address of secondary (U57) Clock generator as follows:
"This I2C bus contains the clock generator U57 at I2C address 0x7C and a clock generator configuration EEPROM U58 at I2C address 0x50".

It doesnt however specify the I2C addressing mode of the U56 (First Clock Source)..
Due to missing schematics of the board, its impossible to lookup manually the (S_A0 / S_A1) pins of the 8T49N241 and/or the the startup content of the EEPROM.
Please clarify the addressing schemes and initial configuration for this device.
Thank you

AUBoard-15P Schematic

Aenerine — Tue, 11 Feb 2025 12:59:22 GMT

Hello,
I am looking for a PDF schematic of the board. It doesnt seem to be publicly available for download.
There is only the Hardware User Guide (V1.3) with various info and description, however I am interested in the raw PDF schematic of the entire board.
The Hardware user guide itself points to the schematic :"... For additional circuitry detail please
reference the AUBoard-15P HDMI RX Interface, HDMI TX Interface, and HDMI MISC Interface
pages in the schematic ... "

https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/auboard-15p-fpga-development-kit

Can somebody please make it publicly available?
Thank you

sd card availibility

nowwalk — Thu, 21 Nov 2024 01:27:01 GMT

If you look at the auboard 15p schematic, you can see that there is no SD card connector. How can I connect the SD card to the auboard 15p? When I searched, there was no fmc board with an SD card connector, and there is one SD card connector board among the mikro click boards, but it can only be used in SPI mode (data 1 bit). I need an SD card connector that can be used in SDIO (data 4 bit) mode. Is there an SD card connector board that can be connected to the auboard 15p?

AUBoard 15P Availability

cores4days — Thu, 26 Sep 2024 04:03:21 GMT

Hi,

The product page says expected to ship late Q3, 2024. Assuming this is calendar year is this still correct? Are we able to pre-order it?

Kind regards

Hi, does any one know how to buy MSC-Q7-MB-EP5-V3

FNM — Wed, 11 Sep 2024 21:03:37 GMT

Hi, does any one know how to buy MSC-Q7-MB-EP5-V3