AUBoard 15P - Recent Threads

FMCOMMS2 FMC on AU15P?

vadimv — Tue, 19 May 2026 12:40:32 GMT

Hello,

Struggling to get the AD9361 to actually pass any sort of data back to the AU15P. The SPI is working ok, i can talk to the chip, but all LVDS data stays at 0. The AU15P J46 jumper is set so things are running on 1.8V as they should, yet there is no LVDS activity at all.

The AU15P uses HD pins for LA_07_P/N, but regardless of how that's pinned out, the other LVDS pairs ought to produce something. Here, IDELAY passes nothing into the FPGA on the receive side.

Have FMC designs worked on this board before? Has AD9361 testing ever occurred?

Now that this board is being replaced, can we get a schematic of the current version?

RE: FMCOMMS2 FMC on AU15P?

iksevas — Sat, 30 May 2026 23:49:04 GMT

You can gain access to the schematic if you are working with your local FAE from an Avnet company. They can put a request in for you.

Generally though, the User Guide in the case of FMC has the information you need for FMC does it not? What’s missing?

RE: FMCOMMS2 FMC on AU15P?

vadimv — Sat, 30 May 2026 18:27:38 GMT

Voltage TP66 -> TP67 is 1.78V, close enough to 1.8V... Seems right.

Not sure what else could be wrong. Trying things on the Alinx card instead.

Guys, you've got to make the schematic available. Obfuscating this is not ok, no other eval board vendor would do this.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 02:49:35 GMT

This is valuable info - will check and report back.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 02:49:17 GMT

Yup, got that - some of the pins are HP though - so they should work even if I can't make a full 0..5 diff pair LVDS (diff pair 5 is HD unfortunately)

RE: FMCOMMS2 FMC on AU15P?

iksevas — Fri, 22 May 2026 02:41:17 GMT

Are you able to measure the bank IO voltage??

You can measure this at TP66 (the voltage) and TP67 (GND).

RE: FMCOMMS2 FMC on AU15P?

iksevas — Fri, 22 May 2026 02:36:30 GMT

IDELAY and ODELAY are not supported for HDIO banks per UG571.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 00:32:29 GMT

I made that fix already, you recommended it in another thread. Swapping the resistors made it such that the FMCOMMS2 comes up, LED is lit, chip can be talked to over SPI and registers can be set. So the AD9361 is up - but the AU15 RX I/O on the FMC interface is completely dead, and that's the part I'm no able to change. Testing the same logic on the Zedboard (ported to 7-series) worked fine...

RE: FMCOMMS2 FMC on AU15P?

iksevas — Wed, 20 May 2026 15:47:50 GMT

It looks like PG_C2M is required for that FMC card to function and Rev 1 of the AUBoard has a BOM issue where the pull-up to enable this is not populated. It is resolved in Rev 2 due out next month.

Vivado version & PCIe XDMA reference

rogroote — Fri, 01 May 2026 11:10:12 GMT

Hi all,

I am looking for a reference PCIe XDMA design (Vivado project + host driver).
Does anyone have a link to a solid / proven PCIe project targeting the AUBoard 15P?
In addition:

Which Vivado version(s) would you recommend for this board and XDMA?
Any known pitfalls or good practices for this specific platform are also welcome.

Thanks in advance.
Kind regards

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 22:50:16 GMT

There 8 are capacitors on the board that are changing values to support Gen 4.

RE: Vivado version & PCIe XDMA reference

rogroote — Sat, 02 May 2026 22:46:31 GMT

Thanks. Our application requires PCIe Gen4 x4 and DDR4 at maximum speed, so upgrading to revision 2 of the board is necessary.

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 03:12:24 GMT

FYI - there is an article that Adam Taylor wrote called Perfecting PCIe on AUBoard I believe which should get you started down the correct path.

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 03:11:21 GMT

I think you can retarget the XDMA reference design to any of the tools for the most part.

two gotchas:

1) generating the PCIe IP requires you to generate GT lanes to target the AUBoard. This differs from the default settings which more than likely were set to a different board. There is a check box on the last page of the IP settings which allows you to override the default so your XDC will actually take effect.

2) Rev 1 of the AUBoard has wrong capacitance value on the PCIe interface to support Gen 4 properly. This is elder to be resolved with a Rev 2 boards available next month.

PCIe SRNS mode

scwest — Mon, 20 Apr 2026 15:06:27 GMT

I have been trying to test pcie with asynchronus clocks. I have used the tutorial on programmable clock sources to update SFP+ clock to be 100MHz and used it as pcie ref clock. I have been having toruble establishing a link.

I wanted to know if the termiantion on the SFP+ clk line would cuase any issues. There could be other factors like incresed loss in the set up cuasing this error, but I just wanted to make sure this was a viable path.

RE: PCIe SRNS mode

scwest — Thu, 23 Apr 2026 17:32:37 GMT

I had done previously. My orginal design was a common clock and then converted it to SRNS. I chnaged the clock to be sourced SFP+ clk and unslected enable slot clock confgiuration. I think that there could other issues within my system causing these errors.

RE: AUBoard 15P SFP+ clock config

iksevas — Thu, 23 Apr 2026 17:19:12 GMT

Yes

AUBoard 15P SFP+ clock config

thill — Wed, 22 Apr 2026 21:14:55 GMT

Hello,

I'm an AMD dedicated FAE at Avnet. My customer recently purchased AUBoard 15P to begin prototyping an SFP+ solution. It appears that the 10G SFP+ clock needs to come from component U56. Quick summary of what I have figured out so far:

U56 = Renesas 8T49N241-998NLGI
U56 provides clock to quad 226 MGTREFCLK0 (HDMI_CLK_8T49N241_N/P)
U56 has an I2C interface accessible by pins R22 (SDA) and R23 (SCL)
U56 expects RST pin connected to G22 to be driven HIGH to be enabled

Is there a bring up and register write sequence we need to apply to U56 via the I2C connection to enable pass through instead of clock recovery, and program it to 156.25MHz for the SFP+ Module? Customer attempted to enable U56 by driving G22 reset pin high but did not see an output.

Is the EEPROM available to the HDMI subsystem (U37) already programmed? They did attempt to apply the clock configuration example design that configures U57 EEPROM to U37 by changing the I2C pinout from B9/A9 (U57/U58 I2C bus) to R22/R23 (HDMI I2C bus) and running the IDT Timing Commander Tool -> EEPROM configuration tool, hopefully this attempted write did not cause U37 EEPROM to become misconfigured. Is there a way to verify U37 is correctly programmed?

Are there any example designs available for this board that use the SFP+ module on quad 226?

Thanks!

Trevor

RE: AUBoard 15P SFP+ clock config

thill — Thu, 23 Apr 2026 17:03:29 GMT

I think I see what I missed, I thought I could only share clocks from one quad away, but it seems you can share clocks 2 quads away if under 16.375 Gb/s. I assume you shared the clock source from quad 224 to quad 226 in your SFP solution?

RE: AUBoard 15P SFP+ clock config

iksevas — Thu, 23 Apr 2026 16:24:05 GMT

The SFP port has been tested at full line rates using the clock generator in the reference design. Not sure why you think you can’t use that clock.

RE: AUBoard 15P SFP+ clock config

thill — Thu, 23 Apr 2026 16:13:28 GMT

That is generally the flow we tried but the write failed. Was the SFP+ Module on this board ever tested? How is the clock for this SFP+ port meant to be configured? It shares a quad with HDMI transceivers and only has access to the HDMI rx recovered clock, and the clock generated by U56. Any more detailed guidance on how to verify structural differences in the memory? Will that involve making modifications to how microblaze is writing to I2C?

RE: AUBoard 15P SFP+ clock config

iksevas — Thu, 23 Apr 2026 16:01:33 GMT

That eeprom is targeted for hdmi EDID data. I’m not certain if the clock generator can be configured from that device. I certainly haven’t tried it as it’s not a use case for us.

Your logic sounds correct, whether it would work is another story. You need to verify structural differences in the memory as well as access differences particularly with reference to the clock generator I2C.

RE: AUBoard 15P SFP+ clock config

thill — Thu, 23 Apr 2026 15:54:58 GMT

Thanks for the reply. This flow configures U58 EEPROM (24AA025T) for the U57 clock generator. We need to configure the U56 clock generator which uses the U37 EEPROM (M24C64-RDW6TP). SFP+ shares a quad with the HDMI transceivers, and so we must use the HDMI clock generated by U56. The second clock generator does not route to quad 226 where SFP+ is bonded. <== For any future readers, this is the misconception. Clocks can be shared from two quads away.

"For this guide, we will focus specifically on configuring the second programmable clock source, U57,
through its associated EEPROM (24AA025T). This EEPROM stores the configuration data that customizes
the clock generator settings, which are then applied during power-up.
The 8T49N241 clock generator is a programmable device that supports both single-ended and differential
outputs. The configuration values for the EEPROM will be generated using the Timing Commander Tool
from Renesas,"

So I think to adjust the example from targeting U58 24AA025T to U37 M24C64-RDW6TP. Is that right? So the flow would be:

1. Change I2C pins from A9/B9 to R22/R23

2. Use the same IDT commander tool to generate config data

3. Program the data via microblaze/I2C?

These EEPROMs are sized differently, and it makes me think the U37 EEPROM has additional data stored in it fro the rest of the HDMI subsystem. Does this example design still apply to the clock generator U56?

RE: PCIe SRNS mode

iksevas — Thu, 23 Apr 2026 14:43:42 GMT

Review the GT settings in your design. The GTs in the PCIe IP provide a default mapping that is different from the AUBoard GT mapping. The last tab in the PCIe IP has an override button that will allow you to set the appropriate pinout constraint to map to the AUBoard.

RE: PCIe SRNS mode

scwest — Thu, 23 Apr 2026 14:39:33 GMT

Currently testing it with PCIe Gen 2. I have measured the clock and the frequency is correct and the peak to peak is ~0.7V which also should be fine.