AUBoard 15P - Recent Threads

OOB - QC test not passed

iulyanov — Wed, 11 Mar 2026 16:44:26 GMT

Hello,

I am working with the AUBoard-15P carrier together with my own custom FMC card. Earlier, my FMC card had a hardware issue that caused voltage drops on the AUBoard 3.3 V rail. I have now removed the FMC card and I am trying to restore the board to a known-good state by reflashing the official Out-of-Box image to the on-board QSPI flash.

I used the OOB package from: http://avnet.me/auboard-15p-dk-oob and programmed the provided au15p_firmware.mcs into QSPI using Vivado Hardware Manager.

After reflashing, the board no longer starts the web-server demo.
Instead, the UART log shows:

AU15P Board SPI Flash Bootloader v1.0 Build on Oct 15 2024
INFO: QC test not passed, launch QC test program now.
Boot application AU15P_TEST.elf
..
XEMacLite detect_phy: PHY detected at address 1.
auto-negotiated link speed: 100

The bootloader launches AU15P_TEST.elf instead of the expected OOB application / web server.

So, my question is

Is the QC/test application source code available, or at least a description of what it checks? I would like to identify whether the earlier FMC-related fault may have damaged some part of the carrier board. I have strong concerns about it.
Maybe I am using an OOB image that is not appropriate for my board version, and the board itself is OK? My board is AUB-15P-DK-PCB-1

Any guidance would be appreciated. Thank you.

RE: OOB - QC test not passed

iulyanov — Mon, 16 Mar 2026 12:38:32 GMT

Hi iksevas,

Thank you. With this file everything worked as expected out-of-the-box. The server started successfully. So, fortunately, my FMC did not damage the carrier.

It would indeed be good to update the online link to the working OOB version. Thanks again for your attention, the issue is now resolved.

RE: OOB - QC test not passed

iksevas — Fri, 13 Mar 2026 18:47:50 GMT

Here is an OOB MCS file that you should be able to program. I will have the team update the MCS file online. Let me know if this works for you.community.element14.com/.../au15p_5F00_oob.zip

RE: OOB - QC test not passed

iksevas — Thu, 12 Mar 2026 22:54:29 GMT

I believe there is a software check that requires the QC Test to pass before programming the Out of box. You won’t be able to pass that test without test equipment.

II’ll get back to you after done review to see if you gave option to program OOB mcs without factory test.

RE: When will rev 2 be available?

iksevas — Fri, 13 Feb 2026 21:38:17 GMT

It is in manufacturing now. It may be this summer before it is available though because of component lead times.

When will rev 2 be available?

dmeads_70 — Thu, 12 Feb 2026 04:34:49 GMT

I am considering this board and have been browsing this forum looking at issues and solutions.

I read about the JTAG level translator and how it does not work properly above 30 *C. I understand this is being worked on for revision 2 of the board.

Wondering when revision 2 will be available?

Thank you!

Controlling AUBoard-15P form Matlab using the JTAG to AXI interface

Umallik — Mon, 02 Feb 2026 16:08:38 GMT

My project requires control of an AUBoard-15 from Matlab (using the Matlab generated JTAG to AXI block). To that end I am required to create a Board definition file using the interface provided in Matlab. Can someone help me with the entries requested below. I do not have access to the schematics. I am not sure how to go about coming up with answers to these questions.

RE: Controlling AUBoard-15P form Matlab using the JTAG to AXI interface

Umallik — Mon, 02 Feb 2026 16:44:30 GMT

Thank you.

RE: Controlling AUBoard-15P form Matlab using the JTAG to AXI interface

iksevas — Mon, 02 Feb 2026 16:39:28 GMT

Take this for what it is worth from AI:

RE: Controlling AUBoard-15P form Matlab using the JTAG to AXI interface

iksevas — Mon, 02 Feb 2026 16:37:13 GMT

There are only two options for JTAG on the AUBoard - the FPGA and the FMC connector. If you are not using the FMC connector, then the FPGA is the only device in the chain. As far as IR length of the FPGA, you more than likely need to dig into some datasheets for the Artix UltraScale+ and if you are using an FMC card, you will need to determine what devices on that card are in the JTAG chain and similarly find their IR length.

RE: How to enable the PG_C2M (power good to mezzanine) signal on the AUBOARD 15P?

iksevas — Wed, 26 Nov 2025 00:13:05 GMT

You have a couple of options here. The PG_C2M circuit looks like the following:

You could use R226 pullup to drive PG_C2M and populate it with something under 1K-ohms. This would pullup PG_C2M when the 3V3_UTIL (which is used to create +FMC_12V). This would get you passed your issue.

A more accurate PG_C2M would be created by using POWER_GOOD on the board which is driven after +VCCO_66_86. The POWER GOOD signal is on 0-ohm RES R590 which is on the back of the board.

The problem here is that the POWER_GOOD R590 resistor is across the board with respect to PG_C2M signal.

How to enable the PG_C2M (power good to mezzanine) signal on the AUBOARD 15P?

alainsan — Fri, 21 Nov 2025 00:56:54 GMT

My assembly is the AUBOARD 15P + Analog Devices AD-FMCOMMS4 RF board plugged in via the FMC connector.
An essential signal on the AUBOARD 15P is the PG_C2M (power good to mezzanine) to enable the power on the RF board.
I could not find any documentation as to how to enable this signal (any jumper, resistor/??)

More generally, the AUBOARD 15P schematics would be extremely helpful.

The D29 LED is off (meaning PG_C2M is 0).

Any help will be greatly appreciated

the auboard_hdmi_pass_thru example design missing directions?

rowanham — Fri, 10 Oct 2025 00:51:53 GMT

I have an aub15p board. I am trying to build the auboard_hdmi_pass_thru example design, but there are no instructions on how to do this. The three pages of documentation don't mention any changes to update the project from the 2023 software to the 2025 software. Is there a document I am missing?

RE: the auboard_hdmi_pass_thru example design missing directions?

iksevas — Mon, 27 Oct 2025 15:46:08 GMT

I don’t have available a design targeting newer tools.

RE: the auboard_hdmi_pass_thru example design missing directions?

mardistal — Mon, 20 Oct 2025 17:22:23 GMT

hello

did you make it work ?

RE: the auboard_hdmi_pass_thru example design missing directions?

mardistal — Mon, 13 Oct 2025 22:46:41 GMT

yes I know, and I used the modified version that use the 8T49N241,but still don't work

if you have something else please let me know,

thanks

RE: the auboard_hdmi_pass_thru example design missing directions?

iksevas — Mon, 13 Oct 2025 22:34:41 GMT

The clock generator is controlled by the reference design and changes frequency depending on the frame rate / resolution used.

RE: the auboard_hdmi_pass_thru example design missing directions?

iksevas — Mon, 13 Oct 2025 22:33:35 GMT

The key is SW modifications to make sure the reference clock circuit is properly accounted for. This is the usage of the 8T49N241 clock chip (if I got the part number correct) versus the reference design SI Labs part..

RE: the auboard_hdmi_pass_thru example design missing directions?

mardistal — Mon, 13 Oct 2025 22:27:36 GMT

Hello could you simply explain how you get this ref design work ,because all my attempts to make it work fail,the board do not detect the hdmi_tx,no clock lock

all my devices work properly,I mean monitor and cable are ok, the design is absolutly identical from the 2023.1 design

I am running the project on Vivado 2025.1

I have to say again that when I am using the elf file and the hardware f file from 2023.1 project it's work,but when I buid the project i have the issue describe above

regards

RE: the auboard_hdmi_pass_thru example design missing directions?

iksevas — Mon, 13 Oct 2025 19:15:34 GMT

This design reference design has not been re-targeted to different tools. It is an HDMI reference design from the tools version used and modified to make it function with the AUBoard. There is not additional documentation outside of what you have seen. Do you have specific questions that I could look into?

AUBoard 15P Vivado Board file issues

gianluca.garoia — Fri, 29 Aug 2025 13:33:41 GMT

Hi,

as from subj, working with AUBoard15P with Vivado 2025.1, seeing the following issues:

1) in IP Integrator Board tab the AUBoard peripherals + reset are present, but the 300 MHz system clock is missing, and trials to insert it form the Vivado Automation (from "Connection Automation" or from the GUI of Clocking Wizard) also fails, these last two case gives the error:

ERROR: [Common 17-69] Command failed: Failed to get scope property. Unknown property 'VLNV'

Manually deifning this clock and manually constraining it in xdc of course owrks, but the question is about the board files and the automation not working: is this a bug of the board file or not? Any workaround about it?

2) By updating the Vivado Board Catalog from the Refresh button, the AUBoard is not present - at least for my installation, where for example the Avnet ZUBoard is correctly present - solution was to manually install the boar file under ~/.Xilinx/Vivado/2025.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2025.1/boards/Avnet

But any clue or better workaround why the Refresh button does not add the AUBoard?

Thaks in advance

RE: AUBoard 15P Vivado Board file issues

gianluca.garoia — Tue, 09 Sep 2025 09:29:04 GMT

Thanks for your feedback.

Best regards

Gianluca

RE: AUBoard 15P Vivado Board file issues

iksevas — Mon, 08 Sep 2025 21:30:12 GMT

Gianluca- Unfortunately, every use case of the design automation cannot be implemented and I apologize for that. As far as a user clock, there are two good targets on the AUBoard. The first is the SYSCLK_P/N particularly if the DDR is unused. Also, you can use DDR and generate clocks from the DDR core to be used by the FABRIC. The frequency of this generated clock is somewhat limited. As a result of this limitation on the available frequencies, we added the HD_CLK_P/N pin pair. This is a programmable clock from a 8T49N241 device. A user can program this clock (there is a reference design on the AUBoard webpage showing them how) to feed an MMCM that they can then use to generate a myriad of fabric clocks. So, there is flexibility in which clock a user may want to utilize. The SYSCLK_P/N is simpler in that you don't have to program the clock.

RE: AUBoard 15P Vivado Board file issues

gianluca.garoia — Mon, 08 Sep 2025 09:48:04 GMT

Thanks for this further information and sorry for my delay in the answer:

I understand this is intended for the DDR interface, and works well in IP Integrator when instantiating the DDR interface.

Question is which clock should be used as "general purpose FPGA system clock for designs without DDR"

Say for example I want to create a MicroBlaze design and generate a 100 MHz system clock for the Microblaze system - from the AUBoard user guide we have these clocks:

I guess it should be the first or the third clock, both are 300 MHz, and both are not really working with the IP integrator automation, as explained in the former of this post.

Of course we can workaround by manually modifiyng, constraining and specifying these clocks, was just to signal that the ready-to-use automations are not working for this usecase, that I see as a quite common one.

Thanks

AUBoard 15P Schematics/FAE contact

sray — Fri, 22 Aug 2025 18:17:44 GMT

AUBoard 15P Schematics

Hello,

I am interested in getting access to the schematics for the AUBoard 15P development board. I am at a stealth startup in Palo Alto, CA and we will be using this development board for FPGA bringup. Having access to these schematics will help guide us in the design-in of this FPGA into our product.

I understand I likely need to get in touch with an Avnet FAE to get access to the schematics. What is the best way to get in contact with the right person? Documentation suggests starting here.

Thanks,
Steve