AUBoard 15P - Recent Threads

RE: Heatsink or Fan Recommendation

emjay26 — Fri, 14 Aug 2026 12:16:13 GMT

Having not received any part or installation recommendations, I did some research on heatsinks and fans over the past week and am including what I learned below, in case it helps any other users of this board.

A special plea to Avnet/Tria for the future: please include a heatsink and fan with this type of evaluation board. This will cover 99% of the typical use cases and still leave users free to replace it with their own custom thermal solution if they choose. Purchasers of this board just want to be able to use it out of the box to its fullest capabilities and not worry about overheating the part. Don't make them become experts in heatsinks and fans or figure out how to install them on this particular board.

Heatsink/fan information:
The FPGA package is 27 mm x 27 mm and the height from the board surface to the top of the package is ~3.3 mm. You're looking for a "BGA heatsink" and can use either a passive heatsink or a heatsink with a fan attached for active cooling. If no fan, either directly attached or nearby, is blowing air on it, a heatsink will rely on natural convection to cool the part. A taller heatsink will have more surface area available for heat transfer to the air. If a fan is directly attached, a shorter heatsink can be used. The fan should be installed so that the air blows directly into the heatsink. A thermal transfer material like a thermal pad is needed between the heatsink and the part. A solution which physically holds the heatsink against the part will allow for the use of thermal pads with better heat transfer properties and will also be more secure mechanically. For this specific board, this would be a plastic holder designed for this part's dimensions, which clips to the underside of the package edge and a spring clip which holds the heatsink firmly against the part, with a thermal pad between them.

Here are a few options in order of increasing thermal performance and cost:
1. Passive heatsink with double-sided thermal tape:
ATS-55270W-C1-R0
2. Passive heatsink with thermal pad and a plastic attachment and spring clip:
ATS-53270R-C1-R0
3. Similar to #2, but with a fan directly attached to the top of the heatsink:
ATS-61270D-C1-R0 (heatsink, thermal pad, clips, fan attachment hardware)
MF25060V1-1000U-A99 (5V, 2 #28 AWG wire leads, 25 x 25 x 6.5 mm fan)
22-01-3037 (Molex fan connector housing)
08-50-0113 (Molex fan connector pins)
Note: a crimping tool capable of working with the #28 AWG fan wires is also required.

Heatsink or Fan Recommendation

emjay26 — Wed, 05 Aug 2026 20:57:27 GMT

The AUBoard 15P FPGA Development Kit doesn't include a heatsink or fan. These parts can get quite hot, so I think some cooling solution is needed for most applications, even if used only in a climate-controlled space at room temperatures. The user guide lists an example heatsink part number (EA-270- H245-T710), but it's not in stock anywhere and shows minimum order quantities of 500. No example is given for a fan or how to attach it, only a description of the fan header. Can you recommend a heatsink or fan that is available for ordering and provide guidance on how to attach it? Thanks.

RE: Heatsink or Fan Recommendation

wolfgangfriedrich — Thu, 06 Aug 2026 14:21:39 GMT

Why not both? You have to do some math first to find a sufficient solution. Measure the part temperature and calculate the die temp. Then pick a solution that is capable of transporting enough heat away to keep the chip in the goldilocks zone.

RE: When will rev 2 be available?

iksevas — Tue, 28 Jul 2026 13:33:12 GMT

All hardware related errata is resolved. The programming of the clock generator still requires the reference design to implement it.

When will rev 2 be available?

dmeads_70 — Thu, 12 Feb 2026 04:34:49 GMT

I am considering this board and have been browsing this forum looking at issues and solutions.

I read about the JTAG level translator and how it does not work properly above 30 *C. I understand this is being worked on for revision 2 of the board.

Wondering when revision 2 will be available?

Thank you!

RE: When will rev 2 be available?

e2kcpu — Mon, 27 Jul 2026 07:22:24 GMT

Excellent, thank you!

But, which changes/errata were implemented?

We have already some boards, don't like to chase know issues between teams...

RE: When will rev 2 be available?

iksevas — Mon, 27 Jul 2026 07:04:54 GMT

AES-AUB-15P-DK-G Avnet Engineering Services | Sub with Evaluation & Development Kits | Avnet AMERICAS

Revision 2 boards are in-stock - these boards resolve errata of Revision 1.

https://www.avnet.com/wcm/connect/047108b6-dfdc-45c6-88d7-d4fc04ff2c20/AUB-15P-DK-ERRATA-V1P3.pdf?MOD=AJPERES&attachment=true&id=1778091366215

RE: When will rev 2 be available?

e2kcpu — Mon, 27 Jul 2026 06:57:34 GMT

It is warm enough now, I guess it is summer :)

What else will be changed on the version 2?

RE: FMCOMMS2 FMC on AU15P?

iksevas — Sat, 30 May 2026 23:49:04 GMT

You can gain access to the schematic if you are working with your local FAE from an Avnet company. They can put a request in for you.

Generally though, the User Guide in the case of FMC has the information you need for FMC does it not? What’s missing?

FMCOMMS2 FMC on AU15P?

vadimv — Tue, 19 May 2026 12:40:32 GMT

Hello,

Struggling to get the AD9361 to actually pass any sort of data back to the AU15P. The SPI is working ok, i can talk to the chip, but all LVDS data stays at 0. The AU15P J46 jumper is set so things are running on 1.8V as they should, yet there is no LVDS activity at all.

The AU15P uses HD pins for LA_07_P/N, but regardless of how that's pinned out, the other LVDS pairs ought to produce something. Here, IDELAY passes nothing into the FPGA on the receive side.

Have FMC designs worked on this board before? Has AD9361 testing ever occurred?

Now that this board is being replaced, can we get a schematic of the current version?

RE: FMCOMMS2 FMC on AU15P?

vadimv — Sat, 30 May 2026 18:27:38 GMT

Voltage TP66 -> TP67 is 1.78V, close enough to 1.8V... Seems right.

Not sure what else could be wrong. Trying things on the Alinx card instead.

Guys, you've got to make the schematic available. Obfuscating this is not ok, no other eval board vendor would do this.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 02:49:35 GMT

This is valuable info - will check and report back.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 02:49:17 GMT

Yup, got that - some of the pins are HP though - so they should work even if I can't make a full 0..5 diff pair LVDS (diff pair 5 is HD unfortunately)

RE: FMCOMMS2 FMC on AU15P?

iksevas — Fri, 22 May 2026 02:41:17 GMT

Are you able to measure the bank IO voltage??

You can measure this at TP66 (the voltage) and TP67 (GND).

RE: FMCOMMS2 FMC on AU15P?

iksevas — Fri, 22 May 2026 02:36:30 GMT

IDELAY and ODELAY are not supported for HDIO banks per UG571.

RE: FMCOMMS2 FMC on AU15P?

vadimv — Fri, 22 May 2026 00:32:29 GMT

I made that fix already, you recommended it in another thread. Swapping the resistors made it such that the FMCOMMS2 comes up, LED is lit, chip can be talked to over SPI and registers can be set. So the AD9361 is up - but the AU15 RX I/O on the FMC interface is completely dead, and that's the part I'm no able to change. Testing the same logic on the Zedboard (ported to 7-series) worked fine...

RE: FMCOMMS2 FMC on AU15P?

iksevas — Wed, 20 May 2026 15:47:50 GMT

It looks like PG_C2M is required for that FMC card to function and Rev 1 of the AUBoard has a BOM issue where the pull-up to enable this is not populated. It is resolved in Rev 2 due out next month.

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 22:50:16 GMT

There 8 are capacitors on the board that are changing values to support Gen 4.

Vivado version & PCIe XDMA reference

rogroote — Fri, 01 May 2026 11:10:12 GMT

Hi all,

I am looking for a reference PCIe XDMA design (Vivado project + host driver).
Does anyone have a link to a solid / proven PCIe project targeting the AUBoard 15P?
In addition:

Which Vivado version(s) would you recommend for this board and XDMA?
Any known pitfalls or good practices for this specific platform are also welcome.

Thanks in advance.
Kind regards

RE: Vivado version & PCIe XDMA reference

rogroote — Sat, 02 May 2026 22:46:31 GMT

Thanks. Our application requires PCIe Gen4 x4 and DDR4 at maximum speed, so upgrading to revision 2 of the board is necessary.

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 03:12:24 GMT

FYI - there is an article that Adam Taylor wrote called Perfecting PCIe on AUBoard I believe which should get you started down the correct path.

RE: Vivado version & PCIe XDMA reference

iksevas — Sat, 02 May 2026 03:11:21 GMT

I think you can retarget the XDMA reference design to any of the tools for the most part.

two gotchas:

1) generating the PCIe IP requires you to generate GT lanes to target the AUBoard. This differs from the default settings which more than likely were set to a different board. There is a check box on the last page of the IP settings which allows you to override the default so your XDC will actually take effect.

2) Rev 1 of the AUBoard has wrong capacitance value on the PCIe interface to support Gen 4 properly. This is elder to be resolved with a Rev 2 boards available next month.

RE: PCIe SRNS mode

scwest — Thu, 23 Apr 2026 17:32:37 GMT

I had done previously. My orginal design was a common clock and then converted it to SRNS. I chnaged the clock to be sourced SFP+ clk and unslected enable slot clock confgiuration. I think that there could other issues within my system causing these errors.

PCIe SRNS mode

scwest — Mon, 20 Apr 2026 15:06:27 GMT

I have been trying to test pcie with asynchronus clocks. I have used the tutorial on programmable clock sources to update SFP+ clock to be 100MHz and used it as pcie ref clock. I have been having toruble establishing a link.

I wanted to know if the termiantion on the SFP+ clk line would cuase any issues. There could be other factors like incresed loss in the set up cuasing this error, but I just wanted to make sure this was a viable path.

RE: AUBoard 15P SFP+ clock config

iksevas — Thu, 23 Apr 2026 17:19:12 GMT

Yes