SD card boot fail: XFSBL_ERROR_SD_F_OPEN

dugurlu over 5 years ago

Hello,

We're currently testing a custom board. the SD card boot fails with the following log:

Xilinx Zynq MP First Stage Boot Loader

Release 2018.3 Jun 5 2020 - 16:31:27

Reset Mode : System Reset

Platform: Silicon (4.0), Cluster ID 0x80000000

Running on A53-0 (64-bit) Processor, Device Name: XCZU7EV

Processor Initialization Done

================= In Stage 2 ============

SD1 Boot Mode

SD: rc= 0

File name is 1:/BOOT.BIN

SD: Unable to open file 1:/BOOT.BIN: 3

XFSBL_ERROR_SD_F_OPEN

Boot Device Initialization failed 0x29

================= In Stage Err ============

Fsbl Error Status: 0x0

Our image can boot on carrier board. We compare power-up sequence of the two board. No improvement.

We tried to slow down the clock from 200MHz to 100MHz. No improvement.

Do you have another idea that we could try?

Top Replies

silva.marcosr 8 months ago +1

Were you able to solve this issue?

drozwood90 over 5 years ago

Hi there,

Have you been able to test against the Avnet EV Carrier Card?
Have you been able to test against the Avnet boot images?

--Dan
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dugurlu over 5 years ago in reply to drozwood90

Yes. I have tested with 2017.4, 2018.2 and 2019.1 prebuild image. No improvement.
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narrucmot over 5 years ago

A query of the Xilinx forums could be helpful here:
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/zcu102-SD-card-boot-fail-XFSBL-ERROR-SD-F-OPEN/td-p/751573
https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/SD-card-boot-fail-XFSBL-ERROR-SD-F-OPEN/td-p/1062487

Are you using a level shifter on your carrier between the XCZU7EV device and the SD card? How is the SD clock terminated?

--Tom
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dugurlu over 5 years ago in reply to narrucmot

We didn't use level shifter between the XCZU7EV device and the SD card. Our design is no different from the carrier board like below.
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narrucmot over 5 years ago in reply to dugurlu

How is the SD card boot interface configured? SD 2.0 or 3.0? A configuration of SD 2.0 (4-bit) is known to work for the Avnet UltraZed-EV SOM + EV Carrier.

--Tom
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dugurlu over 5 years ago in reply to narrucmot

Thanks your reply. Our configuration is below.
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narrucmot over 5 years ago in reply to dugurlu

I notice your SD1 interface does not enable the WP pin on MIO44. I believe this is required for the FSBL to boot. Please consider making this change and rebuild, make a new boot.bin, etc.

--Tom
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dugurlu over 5 years ago in reply to narrucmot

I have tested with wp enable boot image. Still we couldn't boot from sd card.
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wang168506 over 4 years ago in reply to dugurlu

We didn't use level shifter too, How did you solve this problem finnaly? 3Q
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bhfletcher over 4 years ago in reply to wang168506

Have you probed the SD_CLK at the SD Card connector? The SD_CLK termination resistor needs to be physically placed near the Zynq device, and then the value should be tuned to provide the cleanest clock at the SD Card.

Make sure you have read the SD/SDIO section of Chapter 4 in UG583 as a list of 8 PCB-related items relative to SD interface are included.
Bryan
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