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General SD card boot fail: XFSBL_ERROR_SD_F_OPEN
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  • Replies 14 replies
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  • zedboardcmty
Related

SD card boot fail: XFSBL_ERROR_SD_F_OPEN

dugurlu
dugurlu over 2 years ago

Hello,

We're currently testing a custom board. the SD card boot fails with the following log:

Xilinx Zynq MP First Stage Boot Loader

Release 2018.3   Jun  5 2020  -  16:31:27

Reset Mode      :       System Reset

Platform: Silicon (4.0), Cluster ID 0x80000000

Running on A53-0 (64-bit) Processor, Device Name: XCZU7EV

Processor Initialization Done

================= In Stage 2 ============

SD1 Boot Mode

SD: rc= 0

File name is 1:/BOOT.BIN

SD: Unable to open file 1:/BOOT.BIN: 3

                                      XFSBL_ERROR_SD_F_OPEN

Boot Device Initialization failed 0x29

================= In Stage Err ============

Fsbl Error Status: 0x0

 

Our image can boot on carrier board. We compare power-up sequence of the two board. No improvement.

We tried to slow down the clock  from 200MHz to 100MHz. No improvement.

 

Do you have another idea that we could try?

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  • narrucmot
    narrucmot over 2 years ago

    A query of the Xilinx forums could be helpful here:

    https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/zcu102-SD-card-boot-fail-XFSBL-ERROR-SD-F-OPEN/td-p/751573

    https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/SD-card-boot-fail-XFSBL-ERROR-SD-F-OPEN/td-p/1062487

     

    Are you using a level shifter on your carrier between the XCZU7EV device and the SD card?  How is the SD clock terminated?

     

    --Tom

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  • dugurlu
    dugurlu over 2 years ago in reply to narrucmot

    We didn't use level shifter between the XCZU7EV device and the SD card. Our design is no different from the carrier board like below.

     

     

     

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  • narrucmot
    narrucmot over 2 years ago in reply to dugurlu

    How is the SD card boot interface configured?  SD 2.0 or 3.0?  A configuration of SD 2.0 (4-bit) is known to work for the Avnet UltraZed-EV SOM + EV Carrier.

     

    --Tom

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  • dugurlu
    dugurlu over 2 years ago in reply to narrucmot

    Thanks your reply. Our configuration is below.

     

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  • narrucmot
    narrucmot over 2 years ago in reply to dugurlu

    I notice your SD1 interface does not enable the WP pin on MIO44.  I believe this is required for the FSBL to boot.  Please consider making this change and rebuild, make a new boot.bin, etc.

     

    --Tom

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  • dugurlu
    dugurlu over 2 years ago in reply to narrucmot

    I have tested with wp enable boot image. Still we couldn't boot from sd card.

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  • wang168506
    wang168506 11 months ago in reply to dugurlu

    We didn't use level shifter too, How did you solve this problem finnaly?  3Q

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  • bhfletcher
    bhfletcher 11 months ago in reply to wang168506

    Have you probed the SD_CLK at the SD Card connector? The SD_CLK termination resistor needs to be physically placed near the Zynq device, and then the value should be tuned to provide the cleanest clock at the SD Card.

     

    Make sure you have read the SD/SDIO section of Chapter 4 in UG583 as a list of 8 PCB-related items relative to SD interface are included.

    Bryan

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  • wang168506
    wang168506 11 months ago in reply to bhfletcher

    Thank you for your reply.The only difference between  my board and the early  PCB revision  is  the   level shifter   is not on my board. In other words,i use the bank voltage 3V3,and the early revision is 1V8,

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  • wang168506
    wang168506 11 months ago in reply to bhfletcher

    Thank you for your reply.The only difference between  my board and the early  PCB revision  is  the   level shifter   is not on my board. In other words,i use the bank voltage 3V3,and the early revision is 1V8,

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  • narrucmot
    narrucmot 11 months ago in reply to wang168506

    Are you using the SD card that came with your UltraZed-EV SOM, or a different SD card?

     

    What does the device tree description look like for the SD card interface?  You may need to remove the no-1-8-v directive.  This is the SD card node description from the devicetree for the UltraZed-EV from the Avnet meta-avnet git repository showing the edit to be made:

     

    /* SD1 with level shifter */

    &sdhci1 {

    status = "okay";

    max-frequency = <50000000>;

    no-1-8-v;

    }

     

    https://github.com/Avnet/meta-avnet/blob/2020.2/recipes-bsp/device-tree/files/uz7ev-evcc/system-bsp.dtsi#L119

     

    --Tom

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  • wang168506
    wang168506 11 months ago in reply to narrucmot

    3Q,we will try!

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  • mkesh
    mkesh 11 months ago in reply to wang168506

    Were you able to solve this issue?
    I am facing same problem, let us know how you fixed it. Thanks

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